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Author: Yotsuyanagi, M.

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A 10 b 50 MHz pipelined CMOS A/D converter with S/H
1993 / IEEE
By: Yotsuyanagi, M.; Hirata, K.; Etoh, T.;
A 10 b 100 Ms/s pipelined subranging BiCMOS ADC
1993 / IEEE / 0-7803-0987-1
By: Nakadai, N.; Sone, K.; Yotsuyanagi, M.; Sekine, Y.; Ishida, M.; Nishida, Y.;
A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D converter
1995 / IEEE
By: Yotsuyanagi, M.; Sone, K.; Ishida, M.; Yamaguchi, M.; Hasegawa, H.;
A 1.5 V 8b 8 mW BiCMOS video A/D converter
1996 / IEEE / 0-7803-3136-2
By: Yotsuyanagi, M.; Hasegawa, H.; Yamaguchi, M.; Ishida, M.; Kishi, S.; Satoh, M.;
A 2 V 10 b 20 MSample/s mixed-mode subranging CMOS A/D converter
1995 / IEEE / 0-7803-2495-1
By: Yamaguchi, M.; Hasegawa, H.; Yotsuyanagi, M.; Sone, K.; Ishida, M.;
A 3.3 V 51.84 Mb/s 16-CAP transceiver for ATM-LANs
1997 / IEEE / 0-7803-3721-2
By: Yamane, H.; Muraoka, T.; Nishida, Y.; Yamaguchi, M.; Sugimoto, M.; Kariya, H.; Yotsuyanagi, M.; Iwamoto, Y.; Narisawa, T.; Kohno, T.;
A 4.25 GHz BiCMOS clock recovery circuit with an AV-DSPD architecture for NRZ data stream
1997 / IEEE / 0-7803-3721-2
By: Nakamura, S.; Tajima, A.; Kinoshita, Y.; Suemura, Y.; Fukaishi, M.; Yotsuyanagi, M.; Itani, T.; Miyamoto, H.; Henmi, N.; Yamazaki, T.; Suzuki, H.;
A 1.5v Video-Speed Current-Mode Current-Tree A/d Converter
1994 / IEEE / 0-7803-1918-4
By: Hasegawa, H.; Sone, K.; Yamaguchi, M.; Yotsuyanagi, M.;
Design techniques for analog BiCMOS circuits
1994 / IEEE / 0-7803-2117-0
By: Sone, K.; Yotsuyanagi, M.;
An advanced 0.25-/spl mu/m BiCMOS process integration technology for multi-GHz communication LSIs
1997 / IEEE / 0-7803-3916-9
By: Tajima, A.; Fukaishi, M.; Nakamura, S.; Suzuki, H.; Kinoshita, Y.; Yamazaki, T.; Sucmura, Y.; Yotsuyanagi, M.; Henmi, N.; Fujii, H.; Miyamoto, H.; Itani, T.;
A 4.25 Gb/s CMOS fiber channel transceiver with asynchronous binary tree-type demultiplexer and frequency conversion architecture
1998 / IEEE / 0-7803-4344-1
By: Nakamura, K.; Fukaishi, M.; Yotsuyanagi, M.; Kishi, S.; Tsulsui, Y.; Sato, M.;
A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock
1998 / IEEE / 0-7803-4766-8
By: Abiko, H.; Fukaishi, M.; Nakamura, K.; Yotsuyanagi, M.; Matsumoto, A.;
A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture
1998 / IEEE
By: Yotsuyanagi, M.; Kishi, S.; Tsutsui, Y.; Sato, M.; Nakamura, K.; Fukaishi, M.;
A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications
1998 / IEEE / 0-7803-4497-9
By: Tajima, A.; Nakamura, S.; Fukaishi, M.; Yotsuyanagi, M.; Yamazaki, T.; Kinoshita, Y.; Henmi, N.; Miyamoto, H.; Itani, T.; Suzuki, H.; Suemura, Y.;
A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications
1999 / IEEE
By: Yamazaki, T.; Tajima, A.; Nakamura, S.; Fukaishi, M.; Yotsuyanagi, M.; Kinoshita, Y.; Henmi, N.; Miyamoto, H.; Itani, T.; Suzuki, H.; Suemura, Y.;
A CMOS imager with new focal-plane motion detectors
1999 / IEEE / 4-930813-95-6
By: Nagata, T.; Fujimoto, Y.; Okamoto, F.; Yotsuyanagi, M.; Nakashiba, Y.; Hatano, K.; Furumiya, M.;
A 20 Gb/s CMOS multi-channel transmitter and receiver chip set for ultra-high resolution digital display
2000 / IEEE / 0-7803-5853-8
By: Hirota, Y.; Fukaishi, M.; Heiuchi, H.; Nakamura, K.; Nakazawa, Y.; Yotsuyanagi, M.; Hayama, H.; Ikeno, H.;
A CMOS 50% duty cycle repeater using complementary phase blending
2000 / IEEE / 0-7803-6309-4
By: Nakamura, K.; Yotsuyanagi, M.; Nakazawa, Y.; Hirota, Y.; Fukaishi, M.;
A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays
2000 / IEEE
By: Yotsuyanagi, M.; Hayama, H.; Ikeno, H.; Nakazawa, Y.; Fukaishi, M.; Heiuchi, H.; Nakamura, K.; Hirota, Y.;
A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture
2010 / IEEE
By: Sakaguchi, A.; Nakajima, Y.; Yotsuyanagi, M.; Matsumoto, T.; Kato, N.; Ohkido, T.;

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