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Author: Yang, I.Y.

Results

Channel and source/drain engineering in high-performance sub-0.1 /spl mu/m NMOSFETs using X-ray lithography
1994 / IEEE / 0-7803-1921-4
By: Hang Hu; Smith, H.I.; Antoniadis, D.A.; Yang, I.Y.; Su, L.T.;
Back gated CMOS on SOIAS for dynamic threshold voltage control
1995 / IEEE / 0-7803-2700-4
By: Chandrakasan, A.; Vieri, C.; Yang, I.Y.; Antoniadis, D.A.;
Modification of parasitic edge leakage in LOCOS-isolated SOI MOSFETS using back-gate stress
1996 / IEEE / 0-7803-3315-2
By: Antoniadis, A.; Yang, I.Y.; Sherony, M.J.; Doyle, B.S.;
Silicon-on-insulator-with-active-substrate (SOIAS) technology
1996 / IEEE / 0-7803-3315-2
By: Antoniadis, D.A.; Lochtefeld, A.; Yang, I.Y.;
Back-gated CMOS on SOIAS for dynamic threshold voltage control
1997 / IEEE
By: Antoniadis, D.A.; Chandrakasan, A.; Vieri, C.; Yang, I.Y.;
Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay
1998 / IEEE / 0-7803-4770-6
By: De, H.; Veeraraghavan, S.; O'Meara, D.; Dyer, D.; Yuan, C.; Lii, T.; Collins, S.; Reid, K.; Bhat, N.; Misra, V.; Woodruff, R.; Anderson, S.G.H.; Pettinato, C.; Gilbert, P.; Yang, I.Y.;
Reduced gate leakage current and boron penetration of 0.18 /spl mu/m 1.5 V MOSFETs using integrated RTCVD oxynitride gate dielectric
1998 / IEEE / 0-7803-4774-9
By: Gilbert, P.; O'Meara, D.L.; Hsing-Huang Tseng; Hebert, L.; Cotton, R.; Tobin, P.J.; Yang, I.Y.; Hegde, R.; Xin Guo; Wang, V.S.;
Sub-60 nm physical gate length SOI CMOS
1999 / IEEE / 0-7803-5410-9
By: Lin, L.; Leong, M.; Sleight, J.; Smeys, P.; Chen, K.; Yang, I.Y.; Su, L.; Assaderaghi, F.; Crowder, S.; Agnello, P.; Park, H.; Chu, W.; Varekamp, P.; Maciejewski, E.; Fung, S.; Nowak, E.;
Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D
2002 / IEEE / 0-7803-7462-2
By: Lee, B.H.; Mocuta, A.; Welser, J.; Haensch, W.; Agnello, P.; Leobandung, E.; Yang, I.Y.; Ieong, M.; Ku, S.H.; Narasimha, S.; Jenkins, K.A.; Domenicucci, A.; Gribelyuk, M.; Kermel, H.; Sendelbach, M.; Jamin, F.; Mezzapelle, J.; Mitchell, R.M.; Chakravarti, A.; Mocuta, D.; Lavoie, C.; Cabral, C.; Chan, K.; Mo, R.; O'Neil, P.; Rim, K.; Sadana, D.; Bedell, S.; Chen, H.;
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
2004 / IEEE / 0-7803-8684-1
By: Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; van Bentum, R.; Grasshoff, G.; Schwan, C.; Ehrichs, E.; Goad, S.; Buller, J.; Krishnan, S.; Greenlaw, D.; Raab, M.; Kepler, N.; Yang, H.S.; Malik, R.; Narasimha, S.; Li, Y.; Divakaruni, R.; Agnello, P.; Allen, S.; Antreasyan, A.; Arnold, J.C.; Bandy, K.; Belyansky, M.; Bonnoit, A.; Bronner, G.; Chan, V.; Chen, X.; Chen, Z.; Chidambarrao, D.; Chou, A.; Clark, W.; Crowder, S.W.; Engel, B.; Harifuchi, H.; Huang, S.F.; Jagannathan, R.; Jamin, F.F.; Kohyama, Y.; Kuroda, H.; Lai, C.W.; Lee, H.K.; Lee, W.-H.; Lim, E.H.; Lai, W.; Mallikarjunan, A.; Matsumoto, K.; McKnight, A.; Nayak, J.; Ng, H.Y.; Panda, S.; Rengarajan, R.; Steigerwalt, M.; Subbanna, S.; Subramanian, K.; Sudijono, J.; Sudo, G.; Sun, S.-P.; Tessier, B.; Toyoshima, Y.; Tran, P.; Wise, R.; Wong, R.; Yang, I.Y.; Wann, C.H.; Su, L.T.; Horstmann, M.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Salz, H.;

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