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Author: Wong, H.-S.P.

Results

Fabrication and Characterization of Nanoscale NiO Resistance Change Memory (RRAM) Cells With Confined Conduction Paths
2011 / IEEE
By: Wong, H.-S.P.; Byoungil Lee;
Nanoscale Bipolar and Complementary Resistive Switching Memory Based on Amorphous Carbon
2011 / IEEE
By: Javey, A.; Chan, P.C.H.; Shimeng Yu; Hong-Yu Chen; Wong, H.-S.P.; Yi Wu; Takei, K.; Yang Chai;
Investigation of Trap Spacing for the Amorphous State of Phase-Change Memory Devices
2011 / IEEE
By: Kuzum, D.; Jeyasingh, R.G.D.; Wong, H.-S.P.;
Carbon Nanotube Robust Digital VLSI
2012 / IEEE
By: Wong, H.-S.P.; Lan Wei; Hai Wei; Patil, N.; Lin, A.; Jie Zhang; Mitra, S.;
Graphene Interconnect Lifetime: A Reliability Analysis
2012 / IEEE
By: Xiangyu Chen; Wong, H.-S.P.; Hyunjong Chung; Sunae Seo; Seo, D.H.;
Low-Energy Robust Neuromorphic Computation Using Synaptic Devices
2012 / IEEE
By: Shimeng Yu; Jeyasingh, R.G.D.; Kuzum, D.; Wong, H.-S.P.;
Integration of Nanoelectromechanical Relays With Silicon nMOS
2012 / IEEE
By: Soogine Chong; Wong, H.-S.P.; Howe, R.T.; Mitra, S.; Byoungil Lee;
Electrothermal Modeling and Design Strategies for Multibit Phase-Change Memory
2012 / IEEE
By: Jaeho Lee; Jeyasingh, R.G.D.; Zijian Li; Goodson, K.E.; Wong, H.-S.P.; Asheghi, M.;
Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer
2012 / IEEE
By: Takei, K.; Hazeghi, A.; Yang Chai; Wong, H.-S.P.; Javey, A.; Chan, P.C.H.; Hong-Yu Chen;
A SPICE Compact Model of Metal Oxide Resistive Switching Memory With Variations
2012 / IEEE
By: Ximeng Guan; Wong, H.-S.P.; Shimeng Yu;
Thermoelectric Characterization and Power Generation Using a Silicon-on-Insulator Substrate
2012 / IEEE
By: SangBum Kim; Jaeho Lee; Goodson, K.E.; Wong, H.-S.P.; Asheghi, M.; in 't Zandt, M.A.A.; Marconnet, A.;
Low frequency noise in phase change materials
2011 / IEEE / 978-1-4577-0192-4
By: Chroboczek, J.A.; Jeyasingh, R.; Wong, H.-S.P.; Mouis, M.; Ghibaudo, G.;
A 1.4�A reset current phase change memory cell with integrated carbon nanotube electrodes for cross-point memory application
2011 / IEEE / 978-1-4244-9949-6
By: Jeyasingh, R.G.D.; Jiale Liang; Wong, H.-S.P.; Hong-Yu Chen;
Analytical approximation of complex band structures for band-to-band tunneling models
2011 / IEEE / 978-1-61284-418-3
By: Ximeng Guan; Wong, H.-S.P.; Saraswat, K.C.; Donghyun Kim;
First demonstration of phase change memory device using solution processed GeTe nanoparticles
2011 / IEEE / 978-1-4577-0708-7
By: Milliron, D.J.; Caldwell, M.A.; Jeyasingh, R.G.D.; Wong, H.-S.P.;
2D analytical model for the study of NEM relay device scaling
2011 / IEEE / 978-1-61284-418-3
By: Daesung Lee; Soogine Chong; Xiaoying Shen; Wong, H.-S.P.; Howe, R.T.; Parsa, R.;
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated
2011 / IEEE / 978-1-4577-1400-9
By: Lan Wei; Mitra, S.; Jie Zhang; Hai Wei; Patil, N.; Wong, H.-S.P.; Hong-Yu Chen; Shulaker, M.M.; Lin, A.;
Electrical and mechanical characterization of lateral NEMS Switches
2011 / IEEE / 978-2-35500-015-7
By: Ardila, G.; Bouteloup, G.; Montes, L.; Hinchet, R.; Parsa, R.; Wong, H.-S.P.; Howe, R.T.; Akarvardar, K.;
Emerging memory devices
2011 / IEEE / 978-1-4577-1756-7
By: Wong, H.-S.P.;
Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing
2012 / IEEE / 978-1-4673-0772-7
By: Wong, H.-S.P.; Lee, S.; Chen Chen; Mitra, S.; Provine, J.; Howe, R.T.; Daesung Lee; Parsa, R.; Soogine Chong;
Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique
2012 / IEEE / 978-1-4577-2145-8
By: Provine, J.; Chong, S.; Parsa, R.; Lee, W.S.; Watt, J.; Mitra, S.; Chen Chen; Wong, H.-S.P.; Howe, R.T.;
Scaling Challenges for the Cross-Point Resistive Memory Array to Sub-10nm Node - An Interconnect Perspective
2012 / IEEE / 978-1-4673-1081-9
By: Wong, S.S.; Yeh, S.; Jiale Liang; Wong, H.-S.P.;
AlOx-Based Resistive Switching Device with Gradual Resistance Modulation for Neuromorphic Device Application
2012 / IEEE / 978-1-4673-1081-9
By: Yi Wu; Ming-Jinn Tsai; Chen, F.; Pei-Yi Gu; Sum-Min Wang; Heng-Yuan Lee; Yu-Sheng Chen; Wong, H.-S.P.; Shimeng Yu;
Scaling behavior of PCM cells in off-state conduction
2012 / IEEE / 978-1-4577-2084-0
By: Chen, J.; Wong, H.-S.P.; Kang, J.F.; Liu, X.Y.; Jeyasingh, R.G.D.; Deng, Y.X.; Lu, Y.; Gao, B.;
The Trojan-proof chip
2015 / IEEE
By: Mitra, S.; Wong, H.-S.P.; Wong, S.;
Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
1997 / IEEE / 0-7803-4100-7
By: Wong, H.-S.P.; Taur, Y.; Chan, K.K.;
Monitoring hot-carrier degradation in SOI MOSFETs by hot-carrier luminescence techniques
1998 / IEEE
By: Selmi, L.; Sangiorgi, E.; Acovic, A.; Wong, H.-S.P.; Pavesi, M.;
Generalized scale length for two-dimensional effects in MOSFETs
1998 / IEEE
By: Wong, H.-S.P.; Taur, Y.; Frank, D.J.;
Digital Imaging
1998 / IEEE
By: Wong, H.-S.P.; Theuwissen, A.J.P.;
Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
1998 / IEEE / 0-7803-4774-9
By: Frank, D.J.; Wong, H.-S.P.; Solomon, P.M.;
Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model
1998 / IEEE / 0-7803-4774-9
By: Wong, H.-S.P.; Laux, S.E.; Solomon, P.M.; MeiKei Ieong; Chidambarrao, D.;
Nanoscale CMOS
1999 / IEEE
By: Solomon, P.M.; Frank, D.J.; Wong, H.-S.P.; Welser, J.J.; Wann, C.H.J.;
Monte Carlo modeling of threshold variation due to dopant fluctuations
1999 / IEEE / 4-930813-95-6
By: Ieong, M.; Taur, Y.; Frank, D.J.; Wong, H.-S.P.;
Monte Carlo modeling of threshold variation due to dopant fluctuations
1999 / IEEE / 4-930813-93-X
By: Taur, Y.; Frank, D.J.; Wong, H.-S.P.; Ieong, M.;
Simulation of stochastic doping effects in Si MOSFETs
2000 / IEEE / 0-85261-704-6
By: Wong, H.-S.P.; Frank, D.J.;
DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS
2000 / IEEE / 0-7803-6279-9
By: Oldiges, P.; Yuan Taur; Wong, H.-S.P.; MeiKei Ieong; Frank, D.;
Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding
2001 / IEEE / 4-89114-012-7
By: Huang, L.-J.; Wong, H.-S.P.; Anderson, R.M.; Speidell, J.L.; Cordes, S.A.; Mooney, P.M.; Canaperi, D.F.; Koester, S.J.; D'Emic, C.P.; Goma, S.; Chu, J.O.;
Strained Si NMOSFETs for high performance CMOS technology
2001 / IEEE / 4-89114-012-7
By: Ieong, M.; Ronsheim, P.; Kanarsky, T.; Ott, J.; Mooney, P.M.; Grill, A.; Hargrove, M.; Koester, S.; Rim, K.; Chu, J.; Wong, H.-S.P.;
High performance double-gate device technology challenges and opportunities
2002 / IEEE / 0-7695-1561-4
By: Nowak, E.; Wong, H.-S.P.; Ieong, M.; Jones, E.C.; Kedzierski, J.;
Field effect transistors-from silicon MOSFETs to carbon nanotube FETs
2002 / IEEE / 0-7803-7235-2
By: Wong, H.-S.P.;
Soft error rate scaling for emerging SOI technology options
2002 / IEEE / 0-7803-7312-X
By: Bernstein, K.; Oldiges, P.; Wong, H.-S.P.; Ieong, M.; Tang, H.; Dennard, R.; Cannon, E.; Klaasen, B.; Heidel, D.;
Electron and hole mobility enhancement in strained SOI by wafer bonding
2002 / IEEE
By: Chu, J.O.; Lijuan Huang; Wong, H.-S.P.; Anderson, R.M.; Speidell, J.L.; Cordes, S.A.; Mooney, P.M.; Canaperi, D.F.; Koester, S.J.; D'Emic, C.P.; Goma, S.A.;
An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs
2002 / IEEE
By: Wong, H.-S.P.; Jones, E.C.; Leong, M.; Roy, R.; Dokumaci, O.; Ren, Z.; Oldiges, P.; Doris, B.; Hegde, S.; Kanarsky, T.;
Two gates are better than one [double-gate MOSFET process]
2003 / IEEE
By: Ronay, M.; Dokumaci, O.; Cohen, G.M.; Krasnoperova, A.; Jones, E.C.; Chan, K.; Zhang, Y.; Guarini, K.W.; Solomon, P.M.; Wong, H.-S.P.; Benedict, J.; Sicina, R.M.; D'Emic, C.P.; Newbury, J.S.; Kozlowski, P.M.; Treichler, J.; Babich, I.V.; Yoon, J.H.; Petrarca, K.; Boyd, D.C.; Ku, V.; Lavoie, C.; Cabral, C., Jr.; Bucchignano, J.J.; Hovel, H.J.;
Examination of hole mobility in ultra-thin body SOI MOSFETs
2002 / IEEE / 0-7803-7462-2
By: Jones, E.C.; Roy, R.A.; Oldiges, P.; Kanarsky, T.; Dokumaci, O.; Doris, B.; Meikei Ieong; Solomon, P.M.; Zhibin Ren; Wong, H.-S.P.; Haensch, W.; Miller, R.J.;
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
2002 / IEEE / 0-7803-7462-2
By: Carruthers, R.; Cabral, C.; Boyd, D.; Zhang, Y.; Kanarsky, T.; Nowak, E.; Kedzierski, J.; Haensch, W.; Ieong, M.; Wong, H.-S.P.; Cottrell, P.; Fried, D.; Rainey, B.A.; Lee, K.-L.; Krishnan, M.; Canaperi, D.; Wong, K.; Saunders, P.; Benedict, J.; Sullivan, E.; Newbury, J.; Roy, R.; Lavoie, C.; Amos, R.;
Extreme scaling with ultra-thin Si channel MOSFETs
2002 / IEEE / 0-7803-7462-2
By: Leathen Shi; Natzle, W.; Zhibin Ren; Dokumaci, O.; Fen-Fen Jamin; Roy, R.A.; Ying Zhang; Kanarsky, T.; Meikei Ieong; Doris, B.; Haensch, W.; Wong, H.-S.P.; Miller, R.J.; Jones, E.C.; Gribelyuk, M.; Womack, S.; Mocuta, A.; Mezzapelle, J.; Hsiang-Jen Huang;
High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric
2002 / IEEE / 0-7803-7462-2
By: Kozlowski, P.M.; Ott, J.A.; Copel, M.; Chan, K.K.; Okorn-Schmidt, H.; Steen, S.E.; Haensch, W.E.; Jones, E.C.; Huiling Shang; Wong, H.-S.P.; Cordes, S.A.;
Electrical characterization of germanium p-channel MOSFETs
2003 / IEEE
By: Okorn-Schimdt, H.; Shang, H.; Hanesch, W.; Wong, H.-S.P.; Jones, E.C.; Steen, S.; Kozlowski, P.; Ott, J.;
Extension and source/drain design for high-performance FinFET devices
2003 / IEEE
By: Meikei Ieong; Kedzierski, J.; Wong, H.-S.P.; Fried, D.; Nowak, E.; Boyd, D.; Roy, R.; Ying Zhang; Kanarsky, T.S.;
Gate capacitance optimization for arrays of carbon nanotube field-effect transistors
2003 / IEEE / 0-7803-7727-3
By: Miller, R.J.; Oldiges, P.; Wong, H.-S.P.; Xinlin Wang;
Carbon nanotube field effect transistors - fabrication, device physics, and circuit implications
2003 / IEEE / 0-7803-7707-9
By: Wong, H.-S.P.; Avouris, P.; Wind, S.; Martel, R.; Derycke, V.; Appenzeller, J.;
Recent progress in devices and materials for CMOS technology
2003 / IEEE / 0-7803-7765-6
By: Wong, H.-S.P.; Shang, H.; Rim, K.; Ren, Z.; Kedzierski, J.; Jones, E.C.; Ieong, M.; Gusev, E.; Doris, B.;
Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate
2004 / IEEE
By: Babich, I.; D'Emic, C.; Kozlowski, P.; Kam-Leung Lee; Huiling Shang; Sikorski, E.; Guarini, K.; Haensch, W.; Wong, H.-S.P.; Meikei Ieong;
AC characterization of top-gated carbon nanotube field effect transistors
2003 / IEEE / 0-7803-8139-4
By: Jenkins, K.A.; Singh, D.V.; Wong, H.-S.P.; Appenzeller, J.;
Nanoscale science and technology - a device and engineering perspective
2003 / IEEE / 0-7803-7749-4
By: Wong, H.-S.P.;
Frequency response of top-gated carbon nanotube field-effect transistors
2004 / IEEE
By: Jenkins, K.A.; Singh, D.V.; Wong, H.-S.P.; Grill, A.; Neumayer, D.; Appenzeller, J.;
Fabrication of metal gated FinFETs through complete gate silicidation with Ni
2004 / IEEE
By: Wong, H.-S.P.; Ying Zhang; Kanarsky, T.; Meikei Ieong; Kedzierski, J.;
The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance
2005 / IEEE
By: Tsu-Jae King; Hutchby, J.A.; Skotnicki, T.; Boeuf, F.; Wong, H.-S.P.;
Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts
2005 / IEEE / 0-7803-9205-1
By: Wong, H.-S.P.;
Investigation of the performance limits of III-V double-gate n-MOSFETs
2005 / IEEE / 0-7803-9268-X
By: Saeroonter Oh; Donghyun Kim; Tejas Krishnamohan; Abhijit Pethe; Saraswat, K.C.; Yoshio Nishi; Wong, H.-S.P.;
Device and Technology Challenges for Nanoscale CMOS
2006 / IEEE / 0-7695-2523-7
By: Wong, H.-S.P.;
Generalized Phase Change Memory Scaling Rule Analysis
2006 / IEEE / 1-4244-0027-9
By: SangBum Kim; Wong, H.-S.P.;
Editorial
2006 / IEEE
By: Wong, H.-S.P.;
Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities
2006 / IEEE
By: Jie Deng; Wong, H.-S.P.;
Analysis of the Frequency Response of Carbon Nanotube Transistors
2006 / IEEE
By: Wong, H.-S.P.; Close, G.F.; Akinwande, D.;
Schottky-Barrier Carbon Nanotube Field Effect Transistor Modeling
2006 / IEEE / 1-4244-0077-5
By: Wong, H.-S.P.; Krishnamohan, T.; Hazeghi, A.;
Measurability Issues in the Radio-Frequency Characterization of Carbon Nanotubes
2006 / IEEE / 1-4244-0077-5
By: Wong, H.-S.P.; Close, G.F.;
Designing Circuits with Carbon Nanotubes Open Questions and Some Possible Directions
2006 / IEEE / 1-4244-0077-5
By: Wong, H.-S.P.; Mitra, S.; Patil, N.; Jie Deng;
A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors
2006 / IEEE / 1-4244-0404-5
By: Deng, J.; Wong, H.-S.P.;
Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization
2006 / IEEE / 1-59593-389-1
By: Jie Deng; Wong, H.-S.P.; Wan, G.C.; Krishnamohan, T.; Hazeghi; Arash;
Schottky-Barrier Carbon Nanotube Field-Effect Transistor Modeling
2007 / IEEE
By: Hazeghi, A.; Wong, H.-S.P.; Krishnamohan, T.;
A Composite Circuit Model for NDR Devices in Random Access Memory Cells
2007 / IEEE
By: Akinwande, D.; Wong, H.-S.P.;
The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology
2007 / IEEE
By: Keunwoo Kim; Jie Deng; Wong, H.-S.P.; Ching-Te Chuang;
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections
2007 / IEEE / 1-4244-0852-0
By: Patil, N.; Jie Deng; Wong, H.-S.P.; Mitra, S.; Chongwu Zhou; Badmaev, A.; Koungmin Ryu;
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits
2007 / IEEE / 978-1-59593-627-1
By: Mitra, S.; Wong, H.-S.P.; Jie Deng; Patil, N.;
Analysis of Temperature in Phase Change Memory Scaling
2007 / IEEE
By: Wong, H.-S.P.; Kim, S.;
Modeling Carbon Nanotube Sensors
2007 / IEEE
By: Jie Deng; Wong, H.-S.P.; Ghosh, K.;
Impact of a Process Variation on Nanowire and Nanotube Device Performance
2007 / IEEE
By: Lee, T.H.; Okajima, M.; Fujita, S.; Paul, B.C.; Nishi, Y.; Wong, H.-S.P.;
An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory
2007 / IEEE / 978-4-900784-03-1
By: Nishi, Y.; Chidsey, C.E.D.; Ratchford, J.B.; Jagannathan, H.; Wong, H.-S.P.; SangBum Kim; Yuan Zhang; McVittie, J.P.;
Band to Band Tunneling Study in High Mobility Materials : III-V, Si, Ge and strained SiGe
2007 / IEEE / 978-1-4244-1101-6
By: Krishnamohan, T.; Donghyun Kim; Saraswat, K.C.; Wong, H.-S.P.; Smith, L.;
Scaling Properties of Phase Change Materials
2007 / IEEE / 978-1-4244-1361-4
By: Milliron, D.; Wong, H.-S.P.; Caldwell, M.; Yuan Zhang; Cha, J.; Jordan-Sweet, J.; Yi-Chou Chen; Rettner, C.T.; Raoux, S.;
Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic
2008 / IEEE
By: Akarvardar, K.; Wong, H.-S.P.; Howe, R.T.; Ionescu, A.M.; Eggimann, C.; Wan, G.C.; Singh Chauhan, Y.; Tsamados, D.;
An Analytical Derivation of the Density of States, Effective Mass, and Carrier Density for Achiral Carbon Nanotubes
2008 / IEEE
By: Wong, H.-S.P.; Nishi, Y.; Akinwande, D.;
Fabrication and Characterization of Carbon Nanotube Interconnects
2007 / IEEE / 978-1-4244-1507-6
By: Wong, H.-S.P.; Close, G.F.;
Design Considerations for Complementary Nanoelectromechanical Logic Gates
2007 / IEEE / 978-1-4244-1507-6
By: Howe, R.T.; Elata, D.; Akarvardar, K.; Wong, H.-S.P.; Parsa, R.; Peumans, P.; Provine, J.; Yoo, K.; Wan, G.C.;
1-D and 2-D Devices Performance Comparison Including Parasitic Gate Capacitance and Screening Effect
2007 / IEEE / 978-1-4244-1507-6
By: Lan Wei; Wong, H.-S.P.; Jie Deng;
Analytical Model of Carbon Nanotube Electrostatics: Density of States, Effective Mass, Carrier Density, and Quantum Capacitance
2007 / IEEE / 978-1-4244-1507-6
By: Akinwande, D.; Wong, H.-S.P.; Nishi, Y.;
A 0.5 �m pixel frame-transfer CCD image sensor in 110 nm CMOS
2007 / IEEE / 978-1-4244-1507-6
By: El Gamal, A.; Fife, K.; Wong, H.-S.P.;
A 3MPixel Multi-Aperture Image Sensor with 0.7�m Pixels in 0.11�m CMOS
2008 / IEEE / 978-1-4244-2010-0
By: Fife, K.; Wong, H.-S.P.; El Gamal, A.;
Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering
2008 / IEEE / 978-1-4244-1614-1
By: Lan Wei; Jie Deng; Wong, H.-S.P.; Ching-Te Chuang; Keunwoo Kim; Li-Wen Chang;
Assembly and Electrical Characterization of Multiwall Carbon Nanotube Interconnects
2008 / IEEE
By: Wong, H.-S.P.; Close, G.F.;
Research opportunities for nanoscale CMOS
2006 / IEEE / 978-1-4244-0603-6
By: Wong, H.-S.P.;
Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET
2008 / IEEE / 978-1-4244-1802-2
By: Kobayashi, M.; Nishi, Y.; Wong, H.-S.P.; Saraswat, K.; Kinoshita, A.;
Integrated wafer-scale growth and transfer of directional Carbon Nanotubes and misaligned-Carbon-Nanotube-immune logic structures
2008 / IEEE / 978-1-4244-1802-2
By: Lin, A.; Patil, N.; Mitra, S.; Wong, H.-S.P.; Myers, E.R.;
Monolithic Integration of CMOS VLSI and Carbon Nanotubes for Hybrid Nanotechnology Applications
2008 / IEEE
By: Akinwande, D.; Wong, H.-S.P.; Close, G.; Fujita, S.; Paul, B.; Yasuda, S.;
Carbon Nanotube Quantum Capacitance for Nonlinear Terahertz Circuits
2009 / IEEE
By: Wong, H.-S.P.; Nishi, Y.; Akinwande, D.;
Fault-Tolerant Circuit for Carbon Nanotube Transistors with Si-CMOS Hybrid Circuitry
2008 / IEEE / 978-1-4244-2104-6
By: Close, G.F.; Akinwande, D.; Yasuda, S.; Fujita, S.; Paul, B.C.; Wong, H.-S.P.;
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits
2008 / IEEE
By: Jie Deng; Patil, N.; Mitra, S.; Wong, H.-S.P.; Lin, A.;
Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits
2009 / IEEE
By: Mitra, S.; Jie Deng; Patil, N.; Wong, H.-S.P.;

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