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Author: Toyoshima, Y.

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Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation
2011 / IEEE
By: Sasaki, T.; Akutsu, H.; Hokazono, A.; Sonehara, T.; Uchida, H.; Toyoshima, Y.; Inaba, S.; Kawanaka, S.; Tomita, M.;
The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET
2012 / IEEE / 978-1-4673-0847-2
By: Okano, K.; Higashi, Y.; Ohguro, T.; Toyoshima, Y.; Inaba, S.;
Drain avalanche hot hole injection mode on PMOSFETs
1988 / IEEE
By: Iwai, H.; Toyoshima, Y.; Hama, K.; Hayashida, H.; Matsuoka, F.; Maeguchi, K.;
A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology
1991 / IEEE
By: Hayashida, H.; Nagamatsu, M.; Mori, J.; Maeguchi, K.; Hirano, M.; Hashimoto, K.; Toyoshima, Y.; Noda, M.; Tanaka, S.;
Analysis of hot-carrier-induced degradation mode on pMOSFET's
1990 / IEEE
By: Toyoshima, Y.; Hama, K.; Hayashida, H.; Iwai, H.; Matsuoka, F.; Maeguchi, K.;
Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's
1990 / IEEE
By: Maeguchi, K.; Hayashida, H.; Matsuoka, F.; Iwai, H.; Toyoshima, Y.; Kanzaki, K.;
High-speed CMOS I/O buffer circuits
1992 / IEEE
By: Takeda, K.J.; Otaka, S.; Ishibe, M.; Shimizu, S.; Takatsuka, S.; Toyoshima, Y.; Tanaka, S.;
Manufacturable local interconnect technology fully compatible with titanium salicide process
1991 / IEEE / 0-87942-673-X
By: Hayashida, H.; Hashimoto, K.; Suguro, K.; Kunishima, I.; Suizu, Y.; Shinagawa, H.; Toyoshima, Y.;
High-performance 0.5 mu m CMOS technology for logic LSIs with embedded large capacity SRAMs
1991 / IEEE / 0-7803-0243-5
By: Shibata, H.; Matsuno, T.; Matsunaga, T.; Shinagawa, H.; Kasai, K.; Toyoshima, Y.; Hayashida, H.; Yoshinari, H.; Norishima, M.; Eguchi, T.; Hashimoto, K.;
Formal approach to scenario analysis
1994 / IEEE
By: Samuel, J.; Hsia, P.; Chen, C.; Toyoshima, Y.; Kung, D.; Gao, J.;
Precise measurement method of source and drain parasitic resistance and design guideline for scaled MOSFET
1994 / IEEE / 0-7803-1921-4
By: Toyoshima, Y.; Asamura, T.; Azuma, A.; Kakumu, M.;
Change impact identification in object oriented software maintenance
1994 / IEEE / 0-8186-6330-8
By: Gao, J.; Kung, D.; Chen, C.; Toyoshima, Y.; Wen, F.; Hsia, P.;
Behavior-based acceptance testing of software systems: a formal scenario approach
1994 / IEEE / 0-8186-6705-2
By: Hsia, P.; Chen, C.; Toyoshima, Y.; Kung, D.; Samuel, J.; Gao, J.;
On object state testing
1994 / IEEE / 0-8186-6705-2
By: Toyoshima, Y.; Hsia, P.; Gao, J.; Suchak, N.; Kung, D.; Chen, C.;
New dual gate doping process using in-situ boron doped-Si for deep sub-/spl mu/m CMOS device
1993 / IEEE / 0-7803-1450-6
By: Mizushima, I.; Azuma, A.; Eguchi, T.; Hashimoto, K.; Toyoshima, Y.; Shiozawa, J.; Mitani, Y.;
Object state testing for object-oriented programs
1995 / IEEE / 0-8186-7119-X
By: Hsia, P.; Kung, D.; Gao, J.Z.; Chen, C.; Toyoshima, Y.;
A test strategy for object-oriented programs
1995 / IEEE / 0-8186-7119-X
By: Pei Hsia; Gao, J.; Kung, D.; Chen, C.; Toyoshima, Y.;
Object state testing and fault analysis for reliable software systems
1996 / IEEE / 0-8186-7707-4
By: Hsia, P.; Venugopalan, N.; Lu, Y.; Kung, D.; Gao, J.; Chen, C.; Toyoshima, Y.;
Developing an integrated testing environment using the World Wide Web technology
1997 / IEEE / 0-8186-8105-5
By: Chen, C.; Gao, J.Z.; Leung, D.K.; Toyoshima, Y.;
Increase of parasitic resistance of p-MOSFETs due to nitrogen atoms incorporation into silicon substrate by N/sub 2/O-oxynitride gate dielectrics process
1997 / IEEE / 0-7803-4100-7
By: Toyoshima, Y.; Yoshimura, H.; Takayanagi-Takagi, M.;
Highly uniform heteroepitaxy of cobalt silicide by using Co-Ti alloy for sub-quarter micron devices
1998 / IEEE / 0-7803-4770-6
By: Toyoshima, Y.; Miyashita, K.; Ohuchi, K.; Akutsu, H.; Iinuma, T.; Suguro, K.;
Novel Shallow Counter Doping Process and High Performance Buried Channel pMOSFET Using Boron Diffusion Through Oxide
1991 / IEEE
By: Toyoshima, Y.; Hashimoto, K.; Hayashida, H.; Eguchi, T.;
Methodology of MOSFET characteristics fluctuation description using BSIM3v3 SPICE model for statistical circuit simulations
1998 / IEEE / 0-7803-4338-7
By: Kasai, K.; Okayama, Y.; Oishi, A.; Azuma, A.; Toyoshima, Y.;
Object-oriented software testing-some research and development
1998 / IEEE / 0-8186-9221-9
By: Chen, C.; Toyoshima, Y.; Pei Hsia; Kung, D.C.; Gao, J.;
Novel corner rounding process for shallow trench isolation utilizing MSTS (Micro-Structure Transformation of Silicon)
1998 / IEEE / 0-7803-4774-9
By: Toyoshima, Y.; Tsunashima, Y.; Mizushima, I.; Sudo, A.; Matsuda, S.; Yoshimura, H.; Sato, T.; Takegawa, Y.;
Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond
1998 / IEEE / 0-7803-4774-9
By: Nakajima, K.; Azuma, A.; Hiura, Y.; Kohyama, Y.; Suguro, K.; Akasaka, Y.; Toyoshima, Y.; Tsuchida, K.; Honjo, A.; Nitta, H.; Miyano, K.;
Importance of Si-N atomic configuration at the Si/oxynitride interfaces on the performance of scaled MOSFETs
1998 / IEEE / 0-7803-4774-9
By: Takayanagi-Takagi, M.; Toyoshima, Y.;
1Gbps Pure CMOS I/O Buffer Circuits
1991 / IEEE
By: Otaka, S.; Ishibe, A.; Shimizu, S.; Takatsuka, S.; Toyoshima, Y.; Tanaka, S.; Takeda, J.;
Engineering on the Internet for global software production
1999 / IEEE
By: Toyoshima, Y.; Chen, C.; Gao, J.Z.; Leung, D.K.;
Increase of parasitic resistance in shallow p/sup +/ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-/spl mu/m pMOSFET's
1999 / IEEE
By: Matsuoka, F.; Yoshimura, H.; Tanaka, M.; Murakoshi, A.; Inaba, S.; Toyoshima, Y.;
Ultra-thin oxynitride gate dielectrics for 0.18 /spl mu/m CMOS and beyond
1999 / IEEE / 0-9651577-3-3
By: Takayanagi, M.; Toyoshima, Y.;
New optimization guidelines for sub-0.1 /spl mu/m CMOS technologies with 2 nm NO gate oxynitrides
1999 / IEEE / 4-930813-93-X
By: Takayanagi, M.; Fujiwara, M.; Toyoshima, Y.;
Optimized halo structure for 80 nm physical gate CMOS technology with indium and antimony highly angled ion implantation
1999 / IEEE / 0-7803-5410-9
By: Fujiwara, M.; Takayanagi, M.; Yoshimura, H.; Miyashita, K.; Toyoshima, Y.; Nakayama, T.; Adachi, K.;
An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE
1999 / IEEE / 0-7803-5410-9
By: Nakayama, T.; Kawashima, H.; Miyashita, K.; Ohishi, A.; Morifuji, E.; Toyoshima, Y.; Yoshimura, H.;
Copper contamination induced degradation of MOSFET characteristics and reliability
2000 / IEEE / 0-7803-6305-1
By: Yoshimura, H.; Nakayama, T.; Oyamatsu, H.; Iijima, T.; Toyoshima, Y.; Tomita, H.; Yamaguchi, T.; Sakurai, H.; Inohara, M.;
A CMOS technology platform for 0.13 /spl mu/m generation SOC (system on a chip)
2000 / IEEE / 0-7803-6305-1
By: Nishigohri, M.; Nakayama, T.; Yoshimura, H.; Ishiuchi, H.; Toyoshima, Y.; Takato, H.; Inohara, M.; Koike, H.; Habu, M.; Kawashima, H.; Oishi, A.; Morifuji, E.; Miyashita, K.;
Extending gate dielectric scaling limit by NO oxynitride: design and process issues for sub-100 nm technology
2000 / IEEE / 0-7803-6438-4
By: Takayanagi, M.; Fujiwara, M.; Toyoshima, Y.; Shimizu, T.;
Source/drain engineering for sub-100 nm CMOS using selective epitaxial growth technique
2000 / IEEE / 0-7803-6438-4
By: Ohuchi, K.; Hokazono, A.; Toyoshima, Y.; Tsunashima, Y.; Mizushima, I.; Miyano, K.;
Experimental study of gate voltage scaling for TDDB under direct tunneling regime
2001 / IEEE / 0-7803-6587-9
By: Toyoshima, Y.; Takagi, S.; Takayanagi, M.;
In/Sb halo doping and replaced anneal sequence for 80 nm CMOS
2000 / IEEE / 4-89114-008-9
By: Nakayama, T.; Morifuji, E.; Miyashita, K.; Toyoshima, Y.; Yoshimura, H.;
Performance improvement of metal gate CMOS technologies
2001 / IEEE / 4-89114-012-7
By: Azuma, A.; Yamakawa, H.; Matsuda, S.; Toyoshima, Y.;
Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide
2001 / IEEE / 4-89114-012-7
By: Toyoshima, Y.; Nakamura, S.; Ohguro, T.; Momose, H.S.; Iwai, H.; Ishiuchi, H.;
A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides
2001 / IEEE / 4-89114-012-7
By: Ohguro, T.; Toyoshima, Y.; Nakamura, S.; Momose, H.S.; Nagano, T.; Shimizu, T.; Takayanagi, M.; Fujiwara, M.;
Gate voltage dependent model for TDDB lifetime prediction under direct tunneling regime
2001 / IEEE / 4-89114-012-7
By: Toyoshima, Y.; Takagi, S.; Takayanagi, M.;
Combination of germanium preamorphization and sub-keV boron implantation for source/drain extension of pMOSFETs
2001 / IEEE / 4-89114-019-4
By: Adachi, K.; Toyoshima, Y.; Ohuchi, K.;
110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on [110] surface-oriented Si substrate
2002 / IEEE / 0-7803-7312-X
By: Ohguro, T.; Momose, H.S.; Toyoshima, Y.; Nakamura, S.; Kojima, K.;
Improvement of high resistivity substrate for future mixed analog-digital applications
2002 / IEEE / 0-7803-7312-X
By: Kojima, K.; Ohguro, T.; Toyoshima, Y.; Enda, T.; Fukuda, T.; Nitta, S.; Momose, H.S.;
Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate
2002 / IEEE
By: Ishiuchi, H.; Toyoshima, Y.; Nakamura, S.-I.; Ohguro, T.; Momose, H.S.; Iwai, H.;
Characteristics of diffused-stripe InP/InGaAsP/InP lasers emitting around 1.55 µm
1981 / IEEE
By: Toyoshima, Y.; Takahei, K.; Kawaguchi, H.; Iwane, G.; Nagai, H.;
14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide
2002 / IEEE / 0-7803-7462-2
By: Suto, H.; Adachi, K.; Miyano, K.; Yoshimura, H.; Sasaki, T.; Oguma, H.; Yasutake, N.; Mori, S.; Shimizu, T.; Kato, Y.; Magoshi, S.; Watanabe, Y.; Takayanagi, M.; Ohuchi, K.; Hokazono, A.; Ishiuchi, H.; Toyoshima, Y.; Tamaoki, N.; Watanabe, T.; Fukui, H.;
Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics
2002 / IEEE / 0-7803-7462-2
By: Inaba, S.; Ishiuchi, H.; Mori, S.; Sekine, K.; Saki, K.; Suto, H.; Fukui, H.; Nagamine, M.; Fujiwara, M.; Yamamoto, T.; Takayanagi, M.; Mizushima, I.; Okano, K.; Matsuda, S.; Oyamatsu, H.; Tsunashima, Y.; Yamada, S.; Toyoshima, Y.; Shimizu, T.;
Silicon on Depletion Layer FET (SODEL FET) for sub-50 nm high performance CMOS applications: novel channel and S/D profile engineering schemes by selective Si epitaxial growth technology
2002 / IEEE / 0-7803-7462-2
By: Oyamatsu, H.; Ishiuchi, H.; Toyoshima, Y.; Tsunashima, Y.; Inaba, S.; Mizushima, I.; Ohuchi, K.; Hokazono, A.; Miyano, K.;
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide
2002 / IEEE
By: Shibata, H.; Taniguchi, S.; Iinuma, T.; Itani, T.; Murakoshi, A.; Oguma, H.; Mori, S.; Shimizu, T.; Fukui, H.; Suto, H.; Ohuchi, K.; Adachi, K.; Hokazono, A.; Fujiwara, M.; Matsuda, S.; Okano, K.; Inaba, S.; Kudo, T.; Ishiuchi, H.; Toyoshima, Y.; Katsumata, Y.; Suguro, K.; Oyamatsu, H.; Azuma, A.; Takayanagi, M.;
1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate
2003 / IEEE
By: Kojima, K.; Ohguro, T.; Momose, H.S.; Toyoshima, Y.; Nakamura, S.;
S/D extension formation utilizing offset spacer for 65 nm node high performance CMOS
2002 / IEEE / 4-89114-028-3
By: Toyoshima, Y.; Ohuchi, K.; Adachi, K.;
Source/drain engineering for sub 100-nm technology node
2002 / IEEE / 0-7803-7155-0
By: Hokazono, A.; Adachi, K.; Ohuchi, K.; Toyoshima, Y.;
Advanced CMOS device sensitivity to USJ processes and the required accuracy of doping and activation
2002 / IEEE / 0-7803-7155-0
By: Toyoshima, Y.; Oowada, M.; Nakayama, T.; Miyashita, K.; Adachi, K.; Al-Bayati, A.; Matsunaga, Y.; Ito, H.; Spear, J.; Graoui, H.; Ohuchi, K.;
SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology
2004 / IEEE
By: Ishiuchi, H.; Toyoshima, Y.; Ishimaru, K.; Tsunashima, Y.; Oyamatsu, H.; Inaba, S.; Ohuchi, K.; Hokazono, A.; Nagano, H.; Miyano, K.; Mizushima, I.;
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
2004 / IEEE / 0-7803-8684-1
By: Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; van Bentum, R.; Grasshoff, G.; Schwan, C.; Ehrichs, E.; Goad, S.; Buller, J.; Krishnan, S.; Greenlaw, D.; Raab, M.; Kepler, N.; Yang, H.S.; Malik, R.; Narasimha, S.; Li, Y.; Divakaruni, R.; Agnello, P.; Allen, S.; Antreasyan, A.; Arnold, J.C.; Bandy, K.; Belyansky, M.; Bonnoit, A.; Bronner, G.; Chan, V.; Chen, X.; Chen, Z.; Chidambarrao, D.; Chou, A.; Clark, W.; Crowder, S.W.; Engel, B.; Harifuchi, H.; Huang, S.F.; Jagannathan, R.; Jamin, F.F.; Kohyama, Y.; Kuroda, H.; Lai, C.W.; Lee, H.K.; Lee, W.-H.; Lim, E.H.; Lai, W.; Mallikarjunan, A.; Matsumoto, K.; McKnight, A.; Nayak, J.; Ng, H.Y.; Panda, S.; Rengarajan, R.; Steigerwalt, M.; Subbanna, S.; Subramanian, K.; Sudijono, J.; Sudo, G.; Sun, S.-P.; Tessier, B.; Toyoshima, Y.; Tran, P.; Wise, R.; Wong, R.; Yang, I.Y.; Wann, C.H.; Su, L.T.; Horstmann, M.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Salz, H.;
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
2005 / IEEE / 4-900784-00-1
By: Leobandung, E.; Nayakama, H.; Mocuta, D.; Miyamoto, K.; Angyal, M.; Meer, H.V.; McStay, K.; Ahsan, I.; Allen, S.; Azuma, A.; Belyansky, M.; Bentum, R.-V.; Cheng, J.; Chidambarrao, D.; Dirahoui, B.; Fukasawa, M.; Gerhardt, M.; Gribelyuk, M.; Halle, S.; Harifuchi, H.; Harmon, D.; Heaps-Nelson, J.; Hichri, H.; Ida, K.; Inohara, M.; Inouc, I.C.; Jenkins, K.; Kawamura, T.; Kim, B.; Ku, S.-K.; Kumar, M.; Lane, S.; Liebmann, L.; Logan, R.; Melville, I.; Miyashita, K.; Mocuta, A.; O'Neil, P.; Ng, M.-F.; Nogami, T.; Nomura, A.; Norris, C.; Nowak, E.; Ono, M.; Panda, S.; Penny, C.; Radens, C.; Ramachandran, R.; Ray, A.; Rhee, S.-H.; Ryan, D.; Shinohara, T.; Sudo, G.; Sugaya, F.; Strane, J.; Tan, Y.; Tsou, L.; Wang, L.; Wirbeleit, F.; Wu, S.; Yamashita, T.; Yan, H.; Ye, Q.; Yoneyama, D.; Zamdmer, D.; Zhong, H.; Zhu, H.; Zhu, W.; Agnello, P.; Bukofsky, S.; Bronner, G.; Crabbe, E.; Freeman, G.; Huang, S.-F.; Ivers, T.; Kuroda, H.; McHerron, D.; Pellerin, J.; Toyoshima, Y.; Subbanna, S.; Kepler, N.; Su, L.;
Mechanism of hot electron induced degradation in LDD NMOS-FET
1984 / IEEE
By: Toyoshima, Y.; Kanzaki, K.; Wada, M.; Nihira, H.;
Process and design tradeoffs between minimum RC signal propagation delay and interconnect current density and resistance for deep submicrometer ICs
2005 / IEEE
By: Inohara, M.; Toyoshima, Y.;
HfSiON gate dielectric technology for CMOSFET application
2006 / IEEE / 1-4244-0161-5
By: Nagatomo, K.; Nishiyama, A.; Sekine, K.; Sato, M.; Aoyama, T.; Tsunashima, Y.; Eguchi, K.; Watanabe, T.; Koyama, M.; Toyoshima, Y.; Takayanagi, M.; Azuma, A.; Kawanaka, S.; Kobayashi, T.; Tsuchiya, Y.;
FinFET: the prospective multi-gate device for future SoC applications
2006 / IEEE / 1-4244-0302-2
By: Ishimaru, K.; Suguro, K.; Ishida, T.; Kanemura, T.; Aoki, N.; Yagishita, A.; Kawasaki, H.; Kaneko, A.; Izumida, T.; Okano, K.; Inaba, S.; Ishiuchi, H.; Toyoshima, Y.; Tsunashima, Y.; Eguchi, K.;
FinFET: the prospective multi-gate device for future SoC applications
2006 / IEEE / 1-4244-0301-4
By: Aoki, N.; Ishimaru, K.; Kanemura, T.; Yagishita, A.; Ishida, T.; Kawasaki, H.; Kaneko, A.; Izumida, T.; Okano, K.; Inaba, S.; Ishiuchi, H.; Toyoshima, Y.; Tsunashima, Y.; Eguchi, K.; Suguro, K.;
Density Determination of Silicon Spheres Using an Interferometer With Optical Frequency Tuning
2007 / IEEE
By: Mizushima, S.; Azuma, Y.; Fujii, K.; Kuramoto, N.; Toyoshima, Y.;
Guideline for Low-temperature-operation Technique to Extend CMOS Scaling
2006 / IEEE / 1-4244-0438-X
By: Hayashi, Y.; Kajita, A.; Tsumura, K.; Kawanaka, S.; Hokazono, A.; Toyoshima, Y.; Ishimaru, K.; Usui, T.; Tanimoto, H.; Goto, M.; Morooka, T.; Fujiwara, M.; Okano, K.; Inaba, S.; Ohuchi, K.; Aoki, N.; Enda, T.;
High-Performance FinFET with Dopant-Segregated Schottky Source/Drain
2006 / IEEE / 1-4244-0438-X
By: Kaneko, A.; Yagishita, A.; Tsunashima, Y.; Eguchi, K.; Suguro, K.; Ishiuchi, H.; Toyoshima, Y.; Ishimaru, K.; Inaba, S.; Koga, J.; Kinoshita, A.; Aoki, N.; Kanemura, T.; Izumida, T.; Kawasaki, H.; Okano, K.; Mizushima, I.; Matsuo, K.; Omura, M.; Kubota, T.; Yahashi, K.;
Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors
2006 / IEEE / 1-4244-0438-X
By: Nakayama, T.; Toyoshima, Y.; Adachi, K.; Koga, J.; Komoda, T.; Kinoshita, A.; Yamada, S.; Miyashita, K.; Hamaguchi, M.; Hasumi, R.; Kinoshita, T.; Matsuoka, F.;
FinFET Process and Integration Technology for High Performance LSI in 22 nm node and beyond
2007 / IEEE / 1-4244-1103-3
By: Kaneko, A.; Kawasaki, H.; Toyoshima, Y.; Ishimaru, K.; Aoki, N.; Inaba, S.; Yagishita, A.; Tsunashima, Y.; Eguchi, K.; Suguro, K.; Kanemura, T.; Izumida, T.; Okano, K.;
Electrical Characteristics in N- and P-MOSFETS with Slightly Tilted Off-Axis (110) Channel
2007 / IEEE / 83-922632-4-3
By: Ishiuchi, H.; Toyoshima, Y.; Ohguro, T.; Kojima, K.; Yoshitomi, S.; Momose, H.S.;
Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology
2007 / IEEE / 978-4-900784-03-1
By: Itokawa, H.; Mori, S.; Yasutake, N.; Kusunoki, N.; Ishida, T.; Azuma, A.; Mizushima, I.; Toyoshima, Y.; Inaba, S.; Kawanaka, S.; Aoki, N.; Morooka, T.; Okamoto, S.;
R-1: Navigating the Roadmap to 32nm and Beyond: Breaking the Barriers
2007 / IEEE / 978-4-900784-03-1
By: Skotnicki, T.; Patton, G.; Arghavani, R.; Inaba, S.; Liang, M.; Chau, R.; Nishi, Y.; Toyoshima, Y.;
Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond
2007 / IEEE / 978-1-4244-1507-6
By: Ishimaru, K.; Kaneko, A.; Yagishita, A.; Izumida, T.; Aoki, N.; Kawasaki, H.; Inaba, S.; Okano, K.; Toyoshima, Y.;
Profiled Lightly Doped Drain (PLDD) Structure for High Reliable NMOSFETs
1985 / IEEE / 4-930813-09-3
By: Kanzaki, K.; Nihira, N.; Toyoshima, Y.;
An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation
2008 / IEEE / 978-1-4244-2010-0
By: Yamazaki, H.; Otsuka, N.; Miyazaki, T.; Ikehashi, T.; Toyoshima, Y.; Shibata, H.; Suzuki, A.; Sugizaki, Y.; Miyagi, T.; Ohguro, T.; Saito, T.; Miyano, S.; Ogawa, E.;
Process dependence of 0.11 �m RF CMOS on high-resistivity substrate for System on Chip (SOC) application
2008 / IEEE / 978-1-4244-1808-4
By: Momose, H.S.; Momo, N.; Kojima, K.; Ohguro, T.; Toyoshima, Y.;
Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction
2008 / IEEE / 978-1-4244-1802-2
By: Inaba, S.; Kinoshita, T.; Okano, K.; Kaneko, A.; Saitoh, M.; Uchida, K.; Toyoshima, Y.;
Steep channel & Halo profiles utilizing boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond
2008 / IEEE / 978-1-4244-1802-2
By: Kawanaka, S.; Inaba, S.; Mizushima, I.; Kusunoki, N.; Itokawa, H.; Hokazono, A.; Toyoshima, Y.;
Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL
2008 / IEEE / 978-1-4244-1802-2
By: Goto, M.; Tatsumura, K.; Toyoshima, Y.; Eguchi, K.; Koyama, M.; Aoyama, T.; Azuma, A.; Ishida, T.; Inaba, S.; Harakawa, H.; Miyashita, K.; Oguma, H.; Inumiya, S.; Nomachi, A.; Fukushima, T.; Sasaki, T.; Nagatomo, K.; Onoda, H.; Yoshimizu, Y.; Ichihara, R.; Nakajima, K.; Kawanaka, S.;
A Study on aggressive proximity of embedded SiGe with comprehensive SDE engineering for 32 nm-node high-performance pMOSFET technology
2008 / IEEE / 978-1-4244-2363-7
By: Azuma, A.; Mizushima, I.; Kawanaka, S.; Hokazono, A.; Ishida, T.; Miyano, K.; Toyoshima, Y.; Itokawa, H.; Adachi, K.; Kusunoki, N.; Yasutake, N.; Okamoto, H.;
Contact resistance reduction of Pt-incorporated NiSi for continuous CMOS scaling < Atomic level analysis of Pt/B/As distribution within silicide films <
2008 / IEEE / 978-1-4244-2377-4
By: Kawanaka, S.; Hokazono, A.; Sonehara, T.; Toyoshima, Y.; Inaba, S.; Akutsu, H.; Tsujii, H.; Tomita, M.; Uchida, H.; Sasaki, T.;
The study of mobility-tin, trade-off in deeply scaled high-k / metal gate devices and scaling design guideline for 22nm-node generation
2006 / IEEE / 978-1-4244-3308-7
By: Inumiya, S.; Toyoshima, Y.; Kawanaka, S.; Goto, M.; Kusunoki, N.; Inaba, S.; Kinoshita, A.; Tatsumura, K.; Saitoh, M.;
Highly reliable and manufacturable in-line wafer-level hermetic packages for RF MEMS variable capacitor
2009 / IEEE / 978-1-4244-4190-7
By: Yamazaki, H.; Endo, M.; Sugizaki, Y.; Shimooka, Y.; Kojima, A.; Shibata, H.; Ogawa, E.; Toyoshima, Y.; Mori, I.; Miyagi, T.; Obata, S.; Ohguro, T.; Ikehashi, T.;
Compact and Efficient Monte Carlo Method to Reproduce Size Effect on Resistivity in Sub-0.1�m Metallic Interconnects
2009 / IEEE / 978-1-4244-3974-8
By: Matsunaga, N.; Wada, M.; Kurusu, T.; Shibata, H.; Toyoshima, Y.; Aoki, N.; Tanimoto, H.;
Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET
2009 / IEEE / 978-1-4244-4749-7
By: Inaba, S.; Izumida, T.; Okano, K.; Ohguro, T.; Momo, N.; Toyoshima, Y.; Momose, H.S.; Kokubun, K.;
90nm node RF CMOS technology with latch-up immunity on high-resistivity substrate
2009 / IEEE / 978-1-4244-4749-7
By: Toyoshima, Y.; Oda, M.; Higashi, Y.; Momo, N.; Matsuzawa, K.; Momose, H.S.; Ohguro, T.; Kokubun, K.;
Plasma doping and spike annealing technique for steep SDE formation in nano-scale MOSFET
2009 / IEEE / 978-1-4244-6030-4
By: Itani, T.; Inaba, S.; Kawanaka, S.; Tsujii, H.; Miyano, K.; Iinuma, T.; Adachi, K.; Hokazono, A.; Oshima, Y.; Miyata, T.; Toyoshima, Y.;
Steep channel profiles in n/pMOS controlled by boron-doped Si:C layers for continual bulk-CMOS scaling
2009 / IEEE / 978-1-4244-5641-3
By: Hokazono, A.; Toyoshima, Y.; Inaba, S.; Kawanaka, S.; Mizushima, I.; Itokawa, H.;
A 10 ns 54&amp;times;54-bit parallel structured full array multiplier with 0.5 &amp;mu;m CMOS technology
1990 / IEEE
By: Noda, M.; Tanaka, S.; Nagamatsu, M.; Hirano, M.; Toyoshima, Y.; Mori, J.; Maeguchi, K.; Hayashida, H.; Hashimoto, K.;
25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)
2011 / IEEE
By: Inaba, S.; Mizushima, I.; Kusunoki, N.; Itokawa, H.; Hokazono, A.; Toyoshima, Y.; Kawanaka, S.;

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