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Author: Su, L.T.

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A high-performance scalable submicron MOSFET for mixed analog/digital applications
1991 / IEEE / 0-7803-0243-5
By: Yasaitis, J.A.; Su, L.T.; Antoniadis, D.A.;
Annealing-temperature dependence of the thermal conductivity of LPCVD silicon-dioxide layers
1993 / IEEE
By: Flik, M.I.; Goodson, K.E.; Antoniadis, D.A.; Su, L.T.;
Measurement and modeling of self-heating in SOI nMOSFET's
1994 / IEEE
By: Su, L.T.; Flik, M.I.; Goodson, K.E.; Antoniadis, D.A.; Chung, J.E.;
SOI MOSFET effective channel mobility
1994 / IEEE
By: Sherony, M.J.; Antoniadis, D.A.; Chung, J.E.; Su, L.T.;
Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFET's
1994 / IEEE
By: Antoniadis, D.A.; Chung, J.E.; Hang Hu; Sherony, M.J.; Su, L.T.;
Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's
1994 / IEEE
By: Antoniadis, D.A.; Chung, J.; Jacobs, J.B.; Su, L.T.;
Hot-carrier effects in fully-depleted SOI nMOSFETs
1992 / IEEE / 0-7803-0817-4
By: Su, L.T.; Antoniadis, D.A.; Chung, J.E.; Hao Fang;
Measurement and modeling of self-heating effects in SOI nMOSFETs
1992 / IEEE / 0-7803-0817-4
By: Antoniadis, D.A.; Goodson, K.E.; Su, L.T.; Chung, J.E.; Flik, M.I.;
Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFET's
1994 / IEEE
By: Su, L.T.; Sherony, M.J.; Hang Hu; Chung, J.E.; Antoniadis, D.A.;
Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's
1994 / IEEE
By: Su, L.T.; Antoniadis, D.A.; Chung, J.E.; Jacobs, J.B.;
SPICE model and parameters for fully-depleted SOI MOSFET's including self-heating
1994 / IEEE
By: Doyle, B.S.; Arora, N.D.; Antoniadis, D.A.; Su, L.T.; Krakauer, D.B.;
Channel and source/drain engineering in high-performance sub-0.1 /spl mu/m NMOSFETs using X-ray lithography
1994 / IEEE / 0-7803-1921-4
By: Hang Hu; Smith, H.I.; Antoniadis, D.A.; Yang, I.Y.; Su, L.T.;
Comparison of hot-carrier degradation effects in inversion-mode and accumulation-mode fully depleted SOI MOSFETs
1993 / IEEE / 0-7803-1346-1
By: Su, L.T.; Faynot, O.; Antoniadis, D.A.; Auberton-Herve, A.J.; Chung, J.E.; Raynaud, C.; Cristoloveanu, S.;
Inversion electron effective mobility in SOI NMOSFETs
1993 / IEEE / 0-7803-1346-1
By: Chung, J.E.; Su, L.T.; Sherony, M.J.; Antoniadis, D.A.;
Short-channel effects in deep-submicrometer SOI MOSFETS
1993 / IEEE / 0-7803-1346-1
By: Antoniadis, D.A.; Chung, J.E.; Jacobs, J.B.; Su, L.T.;
Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFETs
1993 / IEEE / 0-7803-1450-6
By: Chung, J.E.; Hang Hu; Sherony, M.J.; Su, L.T.; Antoniadis, D.A.;
Reduction of threshold voltage sensitivity in SOI MOSFET's
1995 / IEEE
By: Su, L.T.; Sherony, M.J.; Antoniadis, D.A.; Chung, J.E.;
Tradeoffs of current drive vs. short-channel effect in deep-submicrometer bulk and SOI MOSFETs
1994 / IEEE / 0-7803-2111-1
By: Hang Hu; Su, L.T.; Antoniadis, D.A.; Wei, A.; Sherony, M.J.; Jacobs, J.B.;
Modeling the I-V characteristics of fully-depleted SOI MOSFETs including self-heating
1994 / IEEE / 0-7803-2406-4
By: Antoniadis, D.A.; Doyle, B.S.; Su, L.T.; Arora, N.D.;
Minimization of threshold voltage variation in SOI MOSFETs
1994 / IEEE / 0-7803-2406-4
By: Chung, J.E.; Su, L.T.; Sherony, M.J.; Antoniadis, D.A.;
Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections
1998 / IEEE / 0-7803-4774-9
By: Goldblatt, R.D.; Edelstein, D.C.; Hellner, G.; Surovic, C.W.; Harrer, H.; Deutsch, A.; Biery, G.A.; Su, L.T.; Coteus, P.W.; Crabbe, E.; Foster, D.M.; Greco, N.A.;
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
2004 / IEEE / 0-7803-8684-1
By: Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; van Bentum, R.; Grasshoff, G.; Schwan, C.; Ehrichs, E.; Goad, S.; Buller, J.; Krishnan, S.; Greenlaw, D.; Raab, M.; Kepler, N.; Yang, H.S.; Malik, R.; Narasimha, S.; Li, Y.; Divakaruni, R.; Agnello, P.; Allen, S.; Antreasyan, A.; Arnold, J.C.; Bandy, K.; Belyansky, M.; Bonnoit, A.; Bronner, G.; Chan, V.; Chen, X.; Chen, Z.; Chidambarrao, D.; Chou, A.; Clark, W.; Crowder, S.W.; Engel, B.; Harifuchi, H.; Huang, S.F.; Jagannathan, R.; Jamin, F.F.; Kohyama, Y.; Kuroda, H.; Lai, C.W.; Lee, H.K.; Lee, W.-H.; Lim, E.H.; Lai, W.; Mallikarjunan, A.; Matsumoto, K.; McKnight, A.; Nayak, J.; Ng, H.Y.; Panda, S.; Rengarajan, R.; Steigerwalt, M.; Subbanna, S.; Subramanian, K.; Sudijono, J.; Sudo, G.; Sun, S.-P.; Tessier, B.; Toyoshima, Y.; Tran, P.; Wise, R.; Wong, R.; Yang, I.Y.; Wann, C.H.; Su, L.T.; Horstmann, M.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Salz, H.;
Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
2005 / IEEE / 0-7803-9268-X
By: Horstmann, M.; Wei, A.; Kammler, T.; Hontschel, J.; Bierstedt, H.; Feudel, T.; Frohberg, K.; Gerhardt, M.; Hellmich, A.; Hempel, K.; Hohage, J.; Javorka, P.; Klais, J.; Koerner, G.; Lenski, M.; Neu, A.; Otterbach, R.; Press, P.; Reichel, C.; Trentsch, M.; Trui, B.; Salz, H.; Schaller, M.; Engelmann, H.-J.; Herzog, O.; Ruelke, H.; Hubler, P.; Stephan, R.; Greenlaw, D.; Raab, M.; Kepler, N.; Chen, H.; Chidambarrao, D.; Fried, D.; Holt, J.; Lee, W.; Nii, H.; Panda, S.; Sato, T.; Waite, A.; Liming, S.; Rim, K.; Schepis, D.; Khare, M.; Huang, S.F.; Pellerin, J.; Su, L.T.;

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