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Author: Stierstorfer, R.

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Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond
2006 / IEEE / 1-4244-0005-8
By: Chen, X.; Fang, S.; Davis, C.; Ku, J.H.; Schiml, T.; Sudijono, J.; Yang, I.; Steegen, A.; Coolbough, D.; Hierlemann, M.; Ng, H.; Amos, R.; Sherony, M.; Belyansky, M.; Widodo, J.; Tjoa, T.; Edleman, N.; Kwon, O.; Panda, S.; Yuan, J.; Nguyen, P.; Nivo, N.; Luo, Z.; Chidambarrao, D.; Stierstorfer, R.; Kim, J.; Gao, W.; Dyer, T.; Teh, Y.W.; Tan, S.S.; Ko, Y.; Baiocco, C.; Ajmera, A.; Park, J.;
A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology
2006 / IEEE / 1-4244-0005-8
By: Yuan, J.; Schiml, T.; Hierlemann, M.; Ku, J.; Sudijono, J.; Ng, K.; Barton, K.; Li, J.; Yang, Z.; Stierstorfer, R.; Rovedo, N.; Dyer, T.; Fang, S.; Lee, W.; Luo, Z.; Amos, R.; Hook, T.; Sardesai, V.; Lindsay, R.; Kim, J.; Lee, Y.M.; Tan, S.S.;
Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices
2006 / IEEE / 1-4244-0438-X
By: Han, J.P.; Utomo, H.; Ieong, M.; Sudijono, J.; Ku, J.H.; Shum, D.; Hierlemann, M.; Amos, R.; Chiulli, G.; Lindsay, R.; Kim, S.D.; Loesing, R.; Burns, L.; Turansky, A.; Madan, A.; St Lawrence, B.; Davis, R.; Murphy, R.; Li, J.; Li, J.; Kim, J.J.; Zhuang, H.; Mishra, S.; Schepis, D.; Gutmann, A.; Teo, L.W.; Rovedo, N.; Luo, Z.; Krishnasamy, R.; Stierstorfer, R.; Chong, Y.F.; Fang, S.; Ng, H.; Holt, J.; Adam, T.N.; Kempisty, J.;
High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology
2007 / IEEE / 978-4-900784-03-1
By: Luo, Z.; Rovedo, N.; Ieong, M.; Sudijono, J.; Ku, J.; Hierlemann, M.; Shang, H.; Ng, H.; Tian, C.; Yang, Z.; Vayshenker, A.; Lee, S.; Kim, S.; Lee, H.; Yuan, T.K.J.; Chan, V.; Han, J.; Holt, J.; Park, D.; Kwon, O.; Yan, J.; Fang, S.; Dyer, T.; Teo, L.; Ong, S.; Phoong, B.; Eller, M.; Utomo, H.; Ryou, C.; Wang, H.; Stierstorfer, R.; Clevenger, L.; Kim, S.; Toomey, J.; Sciacca, D.; Li, J.; Wille, W.; Zhao, L.;
Enhanced Stress Proximity Technique with Recessed S/D to Improve Device Performance at 45nm and Beyond
2008 / IEEE / 978-1-4244-1614-1
By: Divakaruni, R.; Chu, S.; Quek, E.; Sudijono, J.; Li, Y.; Ng, H.; Shang, H.; Rovedo, N.; Kim, S.D.; Stierstorfer, R.; Li, J.; Belyansky, M.; Park, J.; Yan, J.; Robinson, R.; Kim, J.J.; Lee, Y.M.; Zhao, L.; Yuan, J.; Fang, S.; Tan, S.S.; Iyer, S.;

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