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Author: Sherony, M.

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PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology

2012 / IEEE / 978-1-4577-2084-0
By: Song, L.; Liang, Y.; Kaste, E.; Divakaruni, R.; Henson, W.K.; Lee, Y.M.; Sherony, M.; Wu, X.; Zhu, C.; Zhang, Q.; Nair, D.; Lee, S.C.; Utomo, H.K.; Greene, B.; Weijtmans, J.W.; Holt, J.; Williams, R.Q.; Brown, J.; Okawa, T.; Josse, E.; Gruensfelder, C.; Pofelski, A.; Onoda, H.; Lai, C.W.; Wallner, T.A.;

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation

1998 / IEEE / 0-7803-4774-9
By: Ajmera, A.; Schepis, D.; Wu, S.; Bolam, R.; Assaderaghi, F.; Rausch, W.; Sleight, J.; Sherony, M.; Leobandung, E.; Shahidi, G.; Davari, B.;

Mainstreaming of the SOI technology

1999 / IEEE / 0-7803-5456-7
By: Bolam, R.; Sherony, M.; Assaderaghi, F.; Ajmera, A.; Shahidi, G.; Chen, T.C.; Davari, B.; Wu, K.; Wagner, L.F.; Sleight, J.W.; Bryant, A.; Schepis, D.; Sadana, D.; Rausch, W.; Moy, D.; Maloney, M.; Lo, H.-S.; Leobandung, E.; Lasky, J.; Hovel, H.; Coffey, M.;

Electrostatic discharge protection in silicon-on-insulator technology

1999 / IEEE / 0-7803-5456-7
By: Warriner, L.; Young, D.; Hui, D.; Voldman, S.; Shahidi, G.; Assaderaghi, F.; Akrout, C.; Rohrer, N.; Sherony, M.; Leobangdung, E.; Rausch, W.; Gross, V.; Howard, J.; Williams, R.;

High performance 0.18 /spl mu/m SOI CMOS technology

1999 / IEEE / 0-7803-5410-9
By: Sadana, D.; Schepis, D.; Chu, W.; Khare, M.; Schulz, R.; Lo, S.-H.; Sherony, M.; Barth, E.; Leobandung, E.; Shahidi, G.; Davari, B.; Chen, T.-C.; Goldblan, R.; Biery, G.; Moy, D.; Assaderaghi, F.; White, F.; Sleight, I.; Boiam, R.;

A partially-depleted SOI compact model - formulation and parameter extraction

2000 / IEEE / 0-7803-6305-1
By: Zamdmer, N.; Sherony, M.; Wagner, L.; Fung, S.K.H.; Assaderaghi, F.; Sleight, J.; Chen, T.C.; Lo, S.H.; Leobandung, E.; Michel, M.;

Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry

2000 / IEEE / 1-58537-018-5
By: Sherony, M.; Howard, J.; Williams, R.; Dreps, D.; Assaderaghi, F.; Young, D.; Hui, D.; Voldman, S.; Shahidi, G.;

Impact of the gate-to-body tunneling current on SOI history effect

2000 / IEEE / 0-7803-6389-2
By: Wagner, L.; Shih-Hsieh Lo; Yang, I.; Sherony, M.; Chen, T.-C.; Zamdmer, N.; Fung, S.K.H.; Assaderaghi, F.; Shahidi, G.;

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

2000 / IEEE / 0-7803-6438-4
By: Fung, S.K.H.; Zamdmer, N.; Assaderaghi, F.; Chen, T.C.; Crowder, S.; Yang, I.; Chuang, C.T.; Shahidi, G.; Joshi, R.; Lo, S.-H.; Sherony, M.; Mocuta, A.; Sleight, J.; Oldiges, P.J.;

Partially depleted silicon-on-insulator (SOI): a device design/modeling and circuit perspective

2000 / IEEE / 964-360-057-2
By: Wu, K.; Lo, S.H.; Sleight, J.; Wagner, L.; Chen, T.-C.; Fung, S.; Shahidi, G.; Sherony, M.; Assaderaghi, F.;

Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM

2001 / IEEE / 4-89114-012-7
By: Joshi, R.V.; Chuang, C.T.; Fung, S.K.H.; Shahidi, G.; Sherony, M.; Yang, I.; Assaderaghi, F.;

A power-efficient 33 GHz 2:1 static frequency divider in 0.12-/spl mu/m SOI CMOS

2003 / IEEE / 0-7803-7694-3
By: Ray, A.; Jonghae Kim; Plouchart, J.-O.; Wagner, L.; Recoules, H.; Sherony, M.; Yue Tan; Zamdmer, N.;

High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

2003 / IEEE / 0-7803-7694-3
By: Kumar, M.; Groves, R.; Sherony, M.; Jenkins, K.A.; Yue Tan; Ray, A.; Fong, N.; Zamdmer, N.; Plouchart, J.-O.; Jonghae Kim; Liang-Hung Lu;

3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

2003 / IEEE / 4-89114-034-8
By: Wagner, L.; Ray, A.; Kumar, M.; Jenkins, K.A.; Meeyoung Yoon; Plouchart, J.-O.; Yue Tan; Liang-Hung Lu; Sherony, M.; Zamdmer, N.; Jonghae Kim;

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate

2003 / IEEE / 1-58113-682-X
By: Ray, A.; Safran, J.; Talbi, M.; Trzcinski, R.; Meeyoung Yoon; Wagner, L.; Sherony, M.; Zamdmer, N.; Plouchart, J.-O.; Jonghae Kim; Yue Tan;

A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology

2003 / IEEE / 1-58113-682-X
By: Zamdmer, N.; Plouchart, J.-O.; Recoules, H.; Jonghae Kim; Yue Tan; Wagner, L.; Ray, A.; Sherony, M.;

A 4-91 GHz distributed amplifier in a standard 0.12 /spl mu/m SOI CMOS microprocessor technology

2003 / IEEE / 0-7803-7842-3
By: Trzcinski, R.; Groves, R.; Yue Tan; Sherony, M.; Liang-Hung Lu; Talbi, M.; Jonghae Kim; Plouchart, J.-O.; Wagner, L.; Zamdmer, N.; Ray, A.;

PD/SOI SRAM performance in presence of gate-to-body tunneling current

2003 / IEEE
By: Joshi, R.V.; Shahidi, G.; Yang, I.; Sherony, M.; Assaderaghi, F.; Fung, S.K.H.; Ching-Te Chuang;

A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-/spl mu/m SOI CMOS technology

2003 / IEEE / 0-7803-7995-0
By: Ray, A.; Jonghae Kim; Plouchart, J.-O.; Wagner, L.; Zamdmer, N.; Talbi, M.; Meeyoung Yoon; Yue Tan; Sherony, M.;

A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology

2004 / IEEE
By: Ray, A.; Talbi, M.; Trzcinski, R.; Groves, R.A.; Tan, Y.; Wagner, L.F.; Liang-Hung Lu; Zamdmer, N.; Jonghae Kim; Plouchart, J.-O.; Sherony, M.;

A 12dBm 320GHz GBW distributed amplifier in a 0.12/spl mu/m SOI CMOS

2004 / IEEE / 0-7803-8267-6
By: Trzcenski, R.; Zamdmer, N.; Plouchart, J.-O.; Jonghae Kim; Wagner, L.; Groves, R.; Safran, J.; Talbi, M.; Tan, Y.; Sherony, M.;

Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI

2004 / IEEE / 0-7803-8497-0
By: Kawanaka, S.; Ketchen, M.B.; Li, Y.; Divakaruni, R.; Clark, W.F.; Yang, I.; Cheek, J.; Kohyama, Y.; Malik, R.; Li, Y.; Ajmera, A.; Mocuta, A.C.; Narasimha, S.; Womack, S.; Waite, A.; Oh, S.-H.; Park, H.; Nakao, T.; Kimura, H.; Rausch, W.; Sudo, G.; Harifuchi, H.; Nii, H.; Utomo, H.; Matsumoto, K.; Fisher, P.; Sherony, M.; Mcstay, K.; Bhasin, R.; Pearson, D.J.; Bhushan, M.;

Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits

2002 / IEEE / 88-900847-8-2
By: Zamdmer, N.; Wagner, L.; Sherony, M.; Ray, A.; O'Neil, P.; Narasimha, S.; Lu, L.-H.; Kim, J.; Plouchart, J.-O.;

65nm cmos technology for low power applications

2005 / IEEE / 0-7803-9268-X
By: Steegen, A.; Mo, R.; Mann, R.; Sun, M.-C.; Eller, M.; Leake, G.; Vietzke, D.; Tilke, A.; Guarin, F.; Fischer, A.; Pompl, T.; Massey, G.; Vayshenker, A.; Tan, W.L.; Ebert, A.; Lin, W.; Gao, W.; Lian, J.; Kim, J.-P.; Wrschka, P.; Yang, J.-H.; Ajmera, A.; Knoefler, R.; Teh, Y.-W.; Jamin, F.; Park, J.E.; Hooper, K.; Griffin, C.; Nguyen, P.; Klee , V.; Ku, V.; Baiocco, C.; Johnson, G.; Tai, L.; Benedict, J.; Scheer, S.; Zhuang, H.; Ramanchandran, V.; Matusiewicz, G.; Lin, Y.-H.; Siew, Y.K.; Zhang, F.; Leong, L.S.; Liew, S.L.; Park, K.C.; Lee, K.-W.; Hong, D.H.; Choi, S.-M.; Kaltalioglu, E.; Kim, S.O.; Naujok, M.; Sherony, M.; Cowley, A.; Thomas, A.; Sudijohno, J.; Schiml, T.; Ku, J.-H.; Yang, I.;

Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

2006 / IEEE / 1-4244-0005-8
By: Chen, X.; Fang, S.; Davis, C.; Ku, J.H.; Schiml, T.; Sudijono, J.; Yang, I.; Steegen, A.; Coolbough, D.; Hierlemann, M.; Ng, H.; Amos, R.; Sherony, M.; Belyansky, M.; Widodo, J.; Tjoa, T.; Edleman, N.; Kwon, O.; Panda, S.; Yuan, J.; Nguyen, P.; Nivo, N.; Luo, Z.; Chidambarrao, D.; Stierstorfer, R.; Kim, J.; Gao, W.; Dyer, T.; Teh, Y.W.; Tan, S.S.; Ko, Y.; Baiocco, C.; Ajmera, A.; Park, J.;

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

2008 / IEEE / 978-1-4244-1802-2
By: Chen, X.; Samavedam, S.; Narayanan, V.; Stein, K.; Hobbs, C.; Baiocco, C.; Li, W.; Jaeger, D.; Zaleski, M.; Yang, H.S.; Kim, N.; Lee, Y.; Zhang, D.; Kang, L.; Chen, J.; Zhuang, H.; Sheikh, A.; Wallner, J.; Aquilino, M.; Han, J.; Jin, Z.; Li, J.; Massey, G.; Kalpat, S.; Jha, R.; Moumen, N.; Mo, R.; Kirshnan, S.; Wang, X.; Chudzik, M.; Chowdhury, M.; Nair, D.; Reddy, C.; Teh, Y.W.; Kothandaraman, C.; Coolbaugh, D.; Pandey, S.; Tekleab, D.; Thean, A.; Sherony, M.; Lage, C.; Sudijono, J.; Lindsay, R.; Ku, J.H.; Khare, M.; Steegen, A.;

Scaling of 32nm low power SRAM with high-K metal gate

2008 / IEEE / 978-1-4244-2377-4
By: Yang, H.S.; Wong, R.; Stiffler, S.; Steegen, A.L.; Sudijono, J.; Pape, J.; Lage, C.; Khare, M.; Sherony, M.; Baiocco, C.V.; Jaeger, D.; Samavedam, S.; Stein, K.; Takasu, Y.; Wallner, J.; Teh, Y.W.; Sun, D.P.; Schiller, C.; Zhuang, L.; Arnaud, F.; Thean, A.; Hasumi, R.; Gao, Y.; Kim, N.S.; Lee, D.H.; Badrudduza, S.; Nair, D.; Ostermayr, M.; Kang, H.; Zhuang, H.; Li, J.; Kang, L.; Chen, X.;

32nm general purpose bulk CMOS technology for high performance applications at low voltage

2008 / IEEE / 978-1-4244-2377-4
By: Arnaud, F.; Steegen, A.; Lee, Y.M.; Lim, K.Y.; Kohler, S.; Chen, J.; Moon, B.K.; Lai, C.W.; Lipinski, M.; Sang, L.; Guarin, F.; Hobbs, C.; Ferreira, P.; Ohuchi, K.; Li, J.; Zhuang, H.; Mora, P.; Zhang, Q.; Nair, D.R.; Lee, D.H.; Chan, K.K.; Satadru, S.; Yang, S.; Koshy, J.; Hayter, W.; Zaleski, M.; Coolbaugh, D.V.; Kim, H.W.; Ee, Y.C.; Sudijono, J.; Thean, A.; Sherony, M.; Samavedam, S.; Khare, M.; Goldberg, C.; Liu, J.;

High-�/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond

2009 / IEEE / 978-1-4244-2784-0
By: Park, D.-G.; Stein, K.; Khare, M.; Divakaruni, R.; Steegen, A.; Lindsay, R.; Sherony, M.; Narayanan, V.; Samavedam, S.; Theon, V.-Y.; Chudzik, M.; Schepis, D.; Haetty, J.; Chowdhury, M.; Kanarsky, T.; Yan, W.; Chen, J.; Zhuang, H.; Jaeger, D.; Chen, X.; Loesing, R.; Tang, T.; Hatzistergos, M.; Moumen, N.; von Arnim, K.; Han, S.; Schruefer, K.; Lee, Y.; Han, J.-P.; Li, W.; Yin, H.; Pacha, C.; Kim, N.; Ostermayr, M.; Eller, M.; Kim, S.; Kim, K.;

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