Your Search Results

Use materials by this author in your textbook!

AcademicPub holds over eight million pieces of educational content – such as case studies and journal articles – for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Author: Saraswat, K.

Results

Simulation for efficient Germanium VCSEL for optical interconnects
2012 / IEEE / 978-1-4577-1619-5
By: Donguk Nam; Saraswat, K.; Miller, D.; Edwards, E.; Sukhdeo, D.;
Demonstration of Electroluminescence from Strained Ge Membrane LED
2012 / IEEE / 978-1-4577-1865-6
By: Donguk Nam; Saraswat, K.; Nishi, Y.; Brongersma, M.; Huang, K.C.; Szu-Lin Cheng; Sukhdeo, D.;
Low-Contact-Resistivity Nickel Germanide Contacts on n+Ge with Phosphorus/Antimony Co-Doping and Schottky Barrier Height Lowering
2012 / IEEE / 978-1-4577-1865-6
By: Maszara, W.P.; Shurong Liang; Gupta, S.; Roy, A.; Nishi, Y.; Lin, J.-Y.J.; Bin Yang; Saraswat, K.;
Photoacoustic measurements of silicon wafer processing temperatures
1989 / IEEE
By: Saraswat, K.; Khuri-Yakub, B.T.; Chou, C.H.; Lee, Y.J.; Moslehi, M.;
A new BiCMOS/CMOS gate comparison/design methodology and supply voltage scaling model
1989 / IEEE / 0-7803-0817-4
By: Saraswat, K.; Raje, P.; Cham, K.;
Control of MMST RTP: repeatability, uniformity, and integration for flexible manufacturing [ICs]
1994 / IEEE
By: Schaper, C.; Kailath, T.; Saraswat, K.; Moslehi, M.;
Flexible relation: an approach for integrating data from multiple, possibly inconsistent databases
1995 / IEEE / 0-8186-6910-1
By: Agarwal, S.; Saraswat, K.; Wiederhold, G.; Keller, A.M.;
Temperature measurement in rapid thermal processing using the acoustic temperature sensor
1996 / IEEE
By: Saraswat, K.; Khuri-Yakub, B.T.; Yong Jin Lee;
An alternative gate electrode material of fully depleted SOI CMOS for low power applications
1997 / IEEE / 0-7803-3938-X
By: Woo, J.C.S.; Saraswat, K.; Wang, A.W.; Hsiao, T.C.;
MBiCMOS: A Device And Circuit Technique Scalable To The Sub-micron, Sub-211 Regime
1991 / IEEE / 0-87942-644-6
By: Plummer, J.; Cham, K.; Ritts, R.; Raje, P.; Saraswat, K.;
Effects of PECVD deposition fluxes on the spatial variation of thin film density of as-deposited SiO/sub 2/ films in interconnect structures
1998 / IEEE / 0-7803-4285-2
By: Plummer, J.; McVittie, J.; Deal, M.; Lee, K.; Saraswat, K.;
R-1 Low Cost Processes (a Vision For Gigabit Manufacturing Toward 2000)
1993 / IEEE
By: Ohmi, T.; Saraswat, K.;
Measurement of VUV induced surface conduction in dielectrics using synchrotron radiation
2000 / IEEE / 0-9651577-4-1
By: Cismaru, C.; Saraswat, K.; McVittie, J.P.; Joshi, M.; Shohet, J.L.;
Direct experimental determination and modeling of VUV induced bulk conduction in dielectrics during plasma processing
2000 / IEEE / 0-9651577-4-1
By: Saraswat, K.; McVittie, J.P.; Joshi, M.;
Development of a physical model of UV induced bulk photoconduction in silicon dioxide and application to charging damage
2002 / IEEE / 0-9651577-7-6
By: Joshi, M.; Saraswat, K.; McVittie, J.P.;
HV silicon-gate MOS integrated circuit for driving piezoelectric tactile displays
1974 / IEEE
By: Meindl, J.; Saraswat, K.;
Invited: Circuit scaling limits for ultra-large-scale integration
1981 / IEEE
By: Meindl, J.; Saraswat, K.; Gerzberg, L.; Ratnakumar, K.;
Performance limitations of devices and interconnects and possible alternatives for nanoelectronics
2004 / IEEE / 0-7695-2093-6
By: Saraswat, K.;
What's beyond the planar MOSFET?
2004 / IEEE / 0-7803-8289-7
By: Mashiko, K.; Lin, M.-R.; Bernstein, K.; Saraswat, K.; Graham, J.; Omura, Y.;
Rump sessions
2004 / IEEE / 0-7803-8287-0
By: Omura, Y.; Lin, M.-R.; Nagata, M.; Bernstein, K.; Saraswat, K.; Graham, J.; Sakamoto, K.;
IIB-3 aluminum alloys with titanium, tungsten, and copper for multilayer interconnections
1984 / IEEE
By: Gardner, D.; Michalka, T.; Saraswat, K.; McVittie, J.; Barbee, T.; Meindl, J.;
IIB-8 high-performance latchup-free CMOS
1984 / IEEE
By: Sangiorgi, E.; Swirhun, S.; Pinto, M.; Rafferty, C.; Saraswat, K.; Dutton, R.; Weeks, A.; Swanson, R.;
Analysis and scaling of Kelvin resistors for extraction of specific contact resistivity
1985 / IEEE
By: Saraswat, K.; Loh, W.M.; Dutton, R.W.;
An accurate method to extract specific contact resistivity using cross-bridge Kelvin resistors
1985 / IEEE
By: Loh, W.M.; Swanson, R.M.; Saraswat, K.; Crabbe, E.; Swirhun, S.E.;
Theoretical Investigation Of Performance In Uniaxially- and Biaxially-Strained Si, SiGe and Ge Double-Gate p-MOSFETs
2006 / IEEE / 1-4244-0438-X
By: Saraswat, K.; Nishi, Y.; Wong, P.; Selberherr, S.; Krishnamohan, T.; Donghyun Kim; Jungemann, C.; Ungersboeck, E.;
Electro-Thermally Coupled Power Optimization for Future Transistors and Its Applications
2007 / IEEE
By: Kapur, P.; Kuo-An Chao, A.; Nishi, Y.; Saraswat, K.; Morifuji, E.;
Investigation of the Performance Limits of III-V Double-Gate n-MOSFETs
2006 / IEEE / 1-4244-0267-0
By: Saeroonter Oh; Donghyun Kim; Krishnamohan, T.; Pethe, A.; Saraswat, K.; Wong, H-S.P.;
High - Mobility, Low Parasitic Resistance Si/Ge/Si Heterostructure Channel Schottky Source/Drain PMOSFETs
2007 / IEEE / 978-1-4244-1101-6
By: Pethe, A.; Saraswat, K.;
On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates
2008 / IEEE
By: Chi On Chui; Martens, K.; Groeseneken, G.; Maes, H.E.; Saraswat, K.; Brammertz, G.; Krishnamohan, T.; Heyns, M.; Meuris, M.; Kuzum, D.; De Jaeger, B.;
Technology and Modeling of Submicron Contacts
1987 / IEEE
By: Dameron, D.; Fu, C-C; Loh, W.; Wright, P.; Saraswat, K.;
Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations
2008 / IEEE / 978-1-4244-1729-2
By: Bersuker, G.; Parat, K.; Kapur, P.; Majhi, P.; Saraswat, K.; Pavan, P.; Verma, S.; Larcher, L.; Padovani, A.;
Performance comparison between copper, carbon nanotube, and optical interconnects
2008 / IEEE / 978-1-4244-1683-7
By: Saraswat, K.; Kyung-Hoae Koo; Kapur, P.; Hoyeol Cho;
Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET
2008 / IEEE / 978-1-4244-1802-2
By: Kobayashi, M.; Nishi, Y.; Wong, H.-S.P.; Saraswat, K.; Kinoshita, A.;
Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and j60mV/dec subthreshold slope
2008 / IEEE / 978-1-4244-2377-4
By: Donghyun Kim; Krishnamohan, T.; Saraswat, K.; Raghunathan, S.;
Comparison of (001), (110) and (111) uniaxial- and biaxial- strained-Ge and strained-Si PMOS DGFETs for all channel orientations: Mobility enhancement, drive current, delay and off-state leakage
2008 / IEEE / 978-1-4244-2377-4
By: Meinerzhagen, B.; Pham, A.-t.; Dinh, T.V.; Donghyun Kim; Krishnamohan, T.; Saraswat, K.; Jungemann, C.;
Fermi-Level Depinning of GaAs for Ohmic Contacts
2008 / IEEE / 978-1-4244-1942-5
By: Donghun Choi; Hu, J.; Wong, H.-S.P.; Saraswat, K.; Harris, J.S.;
High quality GeO2/Ge interface formed by SPA radical oxidation and uniaxial stress engineering for high performance Ge NMOSFETs
2006 / IEEE / 978-1-4244-3308-7
By: Nishi, Y.; Pianetta, P.; Wong, H.-S.P.; Saraswat, K.; Yun Sun; Kope, B.M.; Irisawa, T.; Kobayashi, M.;
Hole Mobility and Its Enhancement with Strain for Technologically Relevant III-V Semiconductors
2009 / IEEE / 978-1-4244-3974-8
By: Saraswat, K.; Krishnamohan, T.; Kim, D.; Nainani, A.;
Conductivity Mismatch and Voltage Dependence of Magnetoresistance in a Semiconductor Spin Injection and Detection Structure
2009 / IEEE / 978-1-4244-3974-8
By: Roy, A.M.; Saraswat, K.; Nikonov, D.E.;
Uniaxial Stress Engineering for High-Performance Ge NMOSFETs
2010 / IEEE
By: Kobayashi, M.; Nishi, Y.; Wong, H.-S.P.; Saraswat, K.; Magyari-Kope, B.; Irisawa, T.;
Investigation of ballistic current in scaled Floating-gate NAND FLASH and a solution
2009 / IEEE / 978-1-4244-5641-3
By: Parat, K.; Krishnamohan, T.; Raghunathan, S.; Saraswat, K.;
On the High-Field Transport and Uniaxial Stress Effect in Ge PFETs
2011 / IEEE
By: Mitard, J.; Kobayashi, M.; Heyns, M.; Nishi, Y.; Saraswat, K.; Meuris, M.; Hoffmann, T.; Irisawa, T.;
BiCMOS gate performance optimization using a unified delay model
1990 / IEEE
By: Saraswat, K.; Cham, K.; Raje, P.;
Electrical Characteristics of Germanium $\hbox{n}^{+}/ \hbox{p}$ Junctions Obtained Using Rapid Thermal Annealing of Coimplanted P and Sb
2011 / IEEE
By: Nishi, Y.; Saraswat, K.; Kamins, T.; Cheng, S.-L.; Thareja, G.;
High n-Type Antimony Dopant Activation in Germanium Using Laser Annealing for $\hbox{n}^{+}/\hbox{p}$ Junction Diode
2011 / IEEE
By: Adams, B.; Chopra, S.; Thareja, G.; Nishi, Y.; Saraswat, K.; Moffatt, S.; Kim, Y.;

Return To Top