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Author: Sakao, M.

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A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)
1990 / IEEE
By: Ishijima, T.; Terada, K.; Sakao, M.; Kubota, T.;
A CMOS/partial-SOI structure for future ULSIs
1988 / IEEE
By: Terada, K.; Sakao, M.; Kubota, T.; Ishijima, T.;
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function
1992 / IEEE
By: Saeki, T.; Sakao, M.; Kunio, T.; Shibahara, K.; Hada, H.; Kasai, N.; Tanigawa, T.; Ishijima, T.; Takada, M.; Aimoto, Y.; Koike, H.; Takeshima, T.; Tanabe, A.; Okuda, T.; Koyama, K.; Murotani, T.; Ohya, S.; Nozue, H.; Miyamoto, H.;
A 30 ns 64 Mb DRAM with built-in self-test and repair function
1992 / IEEE / 0-7803-0573-6
By: Murotani, T.; Koyama, K.; Nozue, H.; Miyamoto, H.; Sakao, M.; Saeki, T.; Tanigawa, T.; Kunio, T.; Ohya, S.; Shibahara, K.; Hada, H.; Kasai, N.; Ishijima, T.; Takada, M.; Aimoto, Y.; Takeshima, T.; Tanabe, A.; Koike, H.; Okuda, T.;
A VLSI chip set for a large-scale parallel inference machine: PIM/m
1993 / IEEE
By: Yamashita, Y.; Machida, H.; Furutani, K.; Yasuda, K.; Ando, H.; Nakashima, H.; Nakaya, M.; Sakao, M.; Nakajima, K.; Takeda, Y.;
A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs
1990 / IEEE
By: Terada, K.; Watanabe, H.; Ikawa, E.; Ishijima, T.; Kasai, N.; Sakao, M.; Kikkawa, T.;
A 1.71-million transistor CMOS CPU chip with a testable cache architecture
1993 / IEEE
By: Hinata, J.; Nishiwaki, Y.; Shirai, K.; Fujioka, I.; Shimotsuma, Y.; Shimizu, T.; Shimazu, Y.; Saito, Y.; Sakao, M.;
A high-density data-path generator with stretchable cells
1994 / IEEE
By: Nakao, H.; Matsumoto, H.; Miyanishi, A.; Hishimaki, H.; Kitada, O.; Tsujihashi, Y.; Sakao, M.; Kayano, S.; Iwade, S.;
Low-temperature integrated process below 500/spl deg/C for thin Ta/sub 2/O/sub 5/ capacitor for giga-bit DRAMs
1994 / IEEE / 0-7803-2111-1
By: Watanabe, H.; Suzuki, H.; Kamiyama, S.; Sakao, M.; Takaishi, Y.;
Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time
1998 / IEEE / 0-7803-4774-9
By: Sakoh, T.; Takaishi, Y.; Komuro, M.; Sakao, M.; Yoshida, K.; Okonogi, K.; Saino, K.; Horiba, S.; Koyama, K.;
A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme
1999 / IEEE / 0-7803-5126-6
By: Takai, Y.; Fujita, M.; Okuda, T.; Kobayashi, Y.; Koyama, K.; Yamaguchi, H.; Hashimoto, T.; Miyamoto, H.; Tanabe, H.; Igeta, M.; Olkawa, T.; Nakanishi, N.; Sekine, J.; Takada, Y.; Uchiyama, S.; Saino, K.; Sakoh, T.; Uchida, T.; Komuro, M.; Matsuo, M.; Takaishi, Y.; Fukase, T.; Horiba, S.; Nagata, K.; Isa, S.; Nakazawa, S.; Hirobe, A.; Ohkubo, H.; Sakao, M.;
A Straight-Line-Trench Isolation And Trench-Gate Transistor (SLIT) Cell For Giga-bit DRAMs
1993 / IEEE
By: Sakao, M.; Takaishi, Y.; Kajiyana, K.; Akimoto, K.; Oguro, S.; Ohya, S.; Shishiguchi, S.;
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme
2000 / IEEE
By: Okuda, T.; Kobayashi, Y.; Koyama, K.; Yamaguchi, H.; Hashimoto, T.; Miyamoto, H.; Tanabe, H.; Igeta, M.; Oikawa, T.; Nakanishi, N.; Sekine, J.; Takada, Y.; Uchiyama, S.; Saino, K.; Sakoh, T.; Uchida, T.; Komuro, M.; Matsuo, M.; Takaishi, Y.; Fukase, T.; Horiba, S.; Sakao, M.; Ohkubo, H.; Hirobe, A.; Nakazawa, S.; Isa, S.; Nagata, K.; Fujita, M.; Takai, Y.;
A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell
1999 / IEEE / 0-7803-5410-9
By: Takeuchi, M.; Taguwa, T.; Kubota, R.; Inoue, K.; Hamada, M.; Kishi, S.; Shirakawa, I.; Nagai, N.; Yamamoto, T.; Sakao, M.; Urabe, K.; Mikagi, K.; Koyanagi, K.; Onishi, S.; Kitamura, H.; Yamaguchi, H.; Kawamoto, H.; Abiko, H.;
A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor
2001 / IEEE / 4-89114-012-7
By: Aoki, Y.; Inoue, K.; Takeuchi, M.; Kishi, S.; Kubota, R.; Hamada, M.; Sakao, M.; Shirai, H.; Yamamoto, T.; Iizuka, T.; Arai, S.; Kitamura, T.; Sakoh, T.;
An analog core memory for pulse-width modulated signal
1966 / IEEE
By: Sakao, M.; Ohno, E.;
Ultra-high-performance 0.13-/spl mu/m embedded DRAM technology using TiN/HfO2/TiN/W capacitor and body-slightly-tied SOI
2002 / IEEE / 0-7803-7462-2
By: Aoki, Y.; Noda, K.; Shirai, H.; Sakoh, T.; Kitamura, T.; Arai, S.; Sakao, M.; Inoue, K.; Takeuchi, M.; Sugimura, H.; Hamada, M.; Wake, T.; Naritake, I.; Iizuka, T.; Yamamoto, T.; Ando, K.; Ueda, T.;
A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)
1987 / IEEE
By: Sakao, M.; Ishijima, T.; Kubota, T.; Kitajima, H.; Hamaguchi, T.; Terada, K.;
Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor
2006 / IEEE / 1-4244-0076-7
By: Inoue, K.; Wake, T.; Arai, S.; Sugimura, H.; Sakoh, T.; Yamagata, Y.; Tanigawa, T.; Shirai, H.; Sakao, M.;
Forced Magnetostriction in Amorphous Gd-Fe Films
1987 / IEEE
By: Itoh, A.; Kawanishi, K.; Sakao, M.; Inoue, F.;

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