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Author: Ritzenthaler, R.

Results

Low frequency noise modeling of SOI MOSFETs using Green's function approach
2011 / IEEE / 978-1-4577-0192-4
By: Faynot, O.; Iniguez, B.; Lime, F.; Ritzenthaler, R.; Pascal, F.; ElHusseini, J.; Bawedin, M.; Armand, J.; Martinez, F.; Valenza, M.;
Charge based compact model for bulk FinFETs
2012 / IEEE / 978-1-4577-1117-6
By: Cerdeira, A.; Claeys, C.; Togo, M.; Franco, J.; Ritzenthaler, R.; Estrada, M.;
Device scaling model for bulk FinFETs
2012 / IEEE / 978-1-4673-0192-3
By: Bhat, N.; Collaert, N.; Chiarella, T.; De Keersgieter, A.; Bhat, K.N.; Mercha, K.; Medury, A.; Ritzenthaler, R.;
Simulation and modeling of nanoscale multiple-gate SOI MOSFETs
2012 / IEEE / 978-83-932075-8-9
By: Lime, F.; Ritzenthaler, R.; Iniguez, B.; Nae, B.;
Low-frequency noise analysis of DRAM peripheral transistors with La cap
2014 / IEEE
By: Simoen, E.; Ritzenthaler, R.; Claeys, C.; Schram, T.; Aoulaiche, M.; Spessot, A.; Fazan, P.; Na, H.-J.; Lee, S.-G.; Son, Y.; Noh, K.B.; Arimura, H.; Horiguchi, N.; Thean, A.;
Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins
2014 / IEEE
By: Mertens, H.; Ritzenthaler, R.; Thean, A.V-Y; Horiguchi, N.; Collaert, N.; Barla, K.; Vandervorst, W.; Groeseneken, G.; Bender, H.; Hikavyy, A.; Franco, J.; Lee, J. W.; Brunco, D. P.; Eneman, G.; Witters, L.; Mitard, J.; Kubicek, S.; Devriendt, K.; Tsvetanova, D.; Milenin, A. P.; Vrancken, C.; Geypen, J.;
Time-dependent variation: A new defect-based prediction methodology
2014 / IEEE
By: Duan, M.; Zhang, J. F.; Asenov, A.; Groeseneken, G.; Thean, A.; Ritzenthaler, R.; Schram, T.; Kaczer, B.; Zhang, W.; Ji, Z.;
Impact of the Substrate Orientation on CHC Reliability in n-FinFETs—Separation of the Various Contributions
2014 / IEEE
By: Crupi, F.; Groeseneken, G.; Horiguchi, N.; Togo, M.; Ritzenthaler, R.; Franco, J.; Cho, M.; Tallarico, A. N.;
Development of a Technique for Characterizing Bias Temperature Instability-Induced Device-to-Device Variation at SRAM-Relevant Conditions
2014 / IEEE
By: Asenov, A.; Groeseneken, G.; Ritzenthaler, R.; Schram, T.; Duan, M.; Zhang, W.D.; Ji, Z.; Zhang, J.F.; Kaczer, B.;
/spl Omega/FETs transistors with TiN metal gate and HfO/sub 2/ down to 10nm
2005 / IEEE / 4-900784-00-1
By: Allain, F.; Papon, A.M.; Garros, X.; Tosti, L.; Vizioz, C.; Brevard, L.; Ritzenthaler, R.; Casse, M.; Faynot, O.; Jahan, C.; Deleonibus, S.; Giffard, B.; Toffoli, A.; Guillaumot, B.; Vinet, M.; Martin, F.; Dansas, H.;
A novel locally engineered (111) V-channel pMOSFET architecture with improved drivability characteristics for low-standby power (LSTP) CMOS applications
2005 / IEEE / 4-900784-00-1
By: Ducroquet, F.; Damlencourt, J.-F.; Ernst, T.; Ritzenthaler, R.; Scheiblin, P.; Weber, O.; Deleonibus, S.; Guillaumot, B.; Toffoli, A.; Andrieu, F.; Brevard, L.; Dansas, H.; Papon, A.-M.; Le Tiec, Y.;
Immunity to substrate effect in advanced /spl Omega/FET devices
2005 / IEEE / 0-7803-9203-5
By: Deleonibus, S.; Brevard, L.; Kuriyama, A.; Jahan, C.; Faynot, O.; Ritzenthaler, R.; Cristoloveanu, S.;
Mobility behavior in narrow �-gateFETs devices
2006 / IEEE / 1-4244-0289-1
By: Barbe, J.-C.; Ernst, T.; Dupre, C.; Faynot, O.; Mescot, X.; Jahan, C.; Ritzenthaler, R.; Cristoloveanu, S.; Deleonibus, S.; Andrieu, F.; Brevard, L.;
Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack
2006 / IEEE / 1-4244-0438-X
By: Ernst, T.; Deleonibus, S.; Ghibaudo, G.; Faynot, O.; Rivallin, P.; Suhm, A.; Guillaumot, B.; Rivoire, M.; Hartmann, J.M.; Rabille, G.; Lafond, D.; Delaye, V.; Andrieu, F.; Borel, S.; Vizioz, C.; Toffoli, A.; De Crecy, F.; Barbe, J.C.; Maffini-Alvaro, V.; Ritzenthaler, R.; Bernard, E.; Isheden, C.; Dupre, C.;
A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs
2007 / IEEE
By: Cristoloveanu, S.; Faynot, O.; Ritzenthaler, R.; Ernst, T.;
Will strain be useful for 10nm quasi-ballistic FDSOI devices? An experimental study
2007 / IEEE / 978-4-900784-03-1
By: Rochette, F.; Bernard, E.; Poiroux, T.; Barral, V.; Deleonibus, S.; Autran, J.L.; Munteanu, D.; LeCarval, G.; Vinet, M.; Grosgeorges, P.; Ritzenthaler, R.; Previtali, B.; Casse, M.; Andrieu, F.; Tosti, L.; Faynot, O.; Barraud, S.;
A novel dual-BBHH erasing scheme to improve endurance and retention performances for localized charge trapping memories
2008 / IEEE / 978-1-4244-2039-1
By: Liyang Pan; Guangjian Shi; Jun Xu; Zhigang Zhang; Lei Sun; Ritzenthaler, R.;
Analytical modeling of the gate tunneling leakage for the determination of adequate high-K dielectrics in 22 nm double-gate SOI MOSFETs
2009 / IEEE / 978-1-4244-6030-4
By: Ritzenthaler, R.; Darbandy, G.; Iiguez, B.; Cerdeira, A.; Estrada, M.; Garduo, S.I.; Lime, F.;
2D compact modeling of the threshold voltage in triple- and Pi-gate transistors
2009 / IEEE / 978-1-4244-6030-4
By: Ritzenthaler, R.; Iiguez, B.; Cristoloveanu, S.; Faynot, O.; Lime, F.;
3D analytical modelling of subthreshold characteristics in Pi-gate FinFET transistors
2010 / IEEE / 978-1-4244-6661-0
By: Lime, F.; Ritzenthaler, R.; Cristoloveanu, S.; Faynot, O.; Iniguez, B.;
The effect of carrier heating on the noise spectral densities for double-gate MOSFET devices
2011 / IEEE / 978-1-4244-7865-1
By: Ritzenthaler, R.; Lazaro, A.; Nae, B.; I�ez, B.;
A simple analytical and explicit compact model for the drain current of UTB SOI MOSFETs
2011 / IEEE / 978-1-4244-7865-1
By: Martinez, F.; Miranda, E.; Iniguez, B.; Ritzenthaler, R.; Lime, F.; Faynot, O.; Pascal, F.;
A surface potential based compact model for lightly doped FD SOI MOSFETs with ultra-thin body
2011 / IEEE / 978-1-4577-0091-0
By: Ritzenthaler, R.; Valenza, M.; Bawedin, M.; Martinez, F.; Husseini, J.E.; Iniguez, B.; Lime, F.;

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