Your Search Results

Use materials by this author in your textbook!

AcademicPub holds over eight million pieces of educational content – such as case studies and journal articles – for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Author: Plummer, J.D.

Results

A novel trench-injector power device with low ON resistance and high switching speed
1988 / IEEE
By: Liu, D.K.Y.; Plummer, J.D.;
Optimization of silicon bipolar transistors for high current gain at low temperatures
1988 / IEEE
By: Woo, J.C.S.; Plummer, J.D.;
Circuit approaches to increasing IGBT switching speed
1988 / IEEE
By: Boisvert, D.M.; Plummer, J.D.; Liu, D.K.Y.;
Surface potential fluctuations in MOS devices induced by the random distribution of channel dopant ions
1988 / IEEE
By: Watt, J.T.; Plummer, J.D.;
Device physics and optimization of conductivity-modulated power MOSFETs
1988 / IEEE
By: Plummer, J.D.; Liu, D.K.Y.;
Characterization of surface mobility in MOS structures containing interfacial cesium ions
1989 / IEEE
By: Fishbein, B.J.; Watt, J.T.; Plummer, J.D.;
The effect of interconnection resistance on the performance enhancement of liquid-nitrogen-cooled CMOS circuits
1989 / IEEE
By: Plummer, J.D.; Watt, J.T.;
Demonstration of a p-channel BICFET in the Ge/sub x/Si/sub 1-x//Si system
1989 / IEEE
By: Taft, R.C.; Iyer, S.S.; Plummer, J.D.;
Characterization of surface mobility on the sidewalls of dry-etched trenches
1988 / IEEE
By: Plummer, J.D.; McVittie, J.P.; Petti, C.J.;
Fabrication of p-channel BICFET in the Ge/sub x/Si/sub 1-x//Si system
1988 / IEEE
By: Plummer, J.D.; Taft, R.C.;
Reduction of lateral phosphorus diffusion in CMOS n-wells
1990 / IEEE
By: Ahn, S.T.; Tiller, W.A.; Plummer, J.D.; Kennel, H.W.;
The complementary insulated-gate bipolar transistor (CIGBT)-a new power switching device
1990 / IEEE
By: Boisvert, D.M.; Plummer, J.D.;
Process simulation high performance bipolar and BiCMOS devices
1989 / IEEE
By: Huang, R.; Griffin, P.B.; Plummer, J.D.;
A closed-form analysis of f/sub T/ for the bipolar transistor down to liquid nitrogen temperature
1989 / IEEE / 0-7803-0817-4
By: Shott, J.D.; Weybright, M.E.; Tamba, N.; Plummer, J.D.;
Advanced heterojunction Ge/sub x/Si/sub 1-x//Si bipolar devices
1989 / IEEE / 0-7803-0817-4
By: Taft, R.C.; Iyer, S.S.; Plummer, J.D.;
An eight-terminal Kelvin-tapped bipolar transistor for extracting parasitic series resistances
1991 / IEEE
By: Plummer, J.D.; Taft, R.C.;
Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossover below 2.5-V supply
1991 / IEEE
By: Raje, P.A.; Ritts, R.B.; Cham, K.M.; Saraswat, K.C.; Plummer, J.D.;
The field-assisted turn-off thyristor: a regenerative device with voltage-controlled turn-off
1992 / IEEE
By: Plummer, J.D.; Petti, C.J.;
Ge/sub x/Si/sub 1-x//silicon inversion-base transistors: theory of operation
1992 / IEEE
By: Plummer, J.D.; Taft, R.C.;
Ge/sub x/Si/sub 1-x//silicon inversion-base transistors: experimental demonstration
1992 / IEEE
By: Iyer, S.S.; Plummer, J.D.; Taft, R.C.;
Device physics and technology of complementary silicon MESFET's for VLSI applications
1991 / IEEE
By: MacWilliams, K.P.; Plummer, J.D.;
MBiCMOS: complex logic and modified gates for improved performance
1991 / IEEE / 0-7803-0103-X
By: Plummer, J.D.; Ritts, R.B.;
Design and analysis of a new conductivity-modulated power MOSFET
1993 / IEEE
By: Liu, D.K.Y.; Plummer, J.D.;
A virtual factory-based environment for semiconductor device development
1992 / IEEE / 0-7803-0680-5
By: Plummer, J.D.; Pan, J.Y.-C.; Wong, W.T.;
A 3-D sidewall flash EPROM cell and memory array
1993 / IEEE
By: Plummer, J.D.; Pein, H.;
A novel DC measurement method for the accurate extraction of bipolar resistive parasitics
1990 / IEEE
By: Plummer, J.D.; Taft, R.C.;
A 3D sidewall flash EPROM cell and memory array
1993 / IEEE
By: Pein, H.; Plummer, J.D.;
A new MOSFET output conductance measurement technique
1993 / IEEE
By: Shott, J.D.; Plummer, J.D.; Faheem Akram, M.;
Measurement of substrate current in SOI MOSFETs
1994 / IEEE
By: Plummer, J.D.; Kuehne, S.C.; Ver Ploeg, E.P.; Nguyen, C.T.; Renteln, P.; Wong, S.S.;
PIN detector arrays and integrated readout circuitry on high-resistivity float-zone silicon
1994 / IEEE
By: Snoeys, W.; Kenney, C.; Parker, S.; Plummer, J.D.;
Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's
1994 / IEEE
By: Nguyen, C.T.; Ver Ploeg, E.P.; Plummer, J.D.; Wong, S.S.;
A simple EEPROM cell using twin polysilicon thin film transistors
1994 / IEEE
By: Saraswat, K.C.; Tiemin Zhao; Mino Cao; Plummer, J.D.;
SOI LIGBT devices with a dual P-well implant for improved latching characteristics
1993 / IEEE / 0-7803-1313-5
By: Plummer, J.D.; Disney, D.R.;
Lateral depletion-mode thyristors in SOI substrates
1993 / IEEE / 0-7803-1313-5
By: Disney, D.R.; Plummer, J.D.;
Elimination of bipolar-induced breakdown in fully-depleted SOI MOSFETs
1992 / IEEE / 0-7803-0817-4
By: Ver Ploeg, E.P.; Watanabe, T.; Kistler, N.A.; Woos, J.C.S.; Plummer, J.D.;
Kinetics of high concentration arsenic deactivation at moderate to low temperatures
1992 / IEEE / 0-7803-0817-4
By: Plummer, J.D.; Carey, P.G.; Griffin, P.B.; Rousseau, P.M.; Luning, S.;
AC characterization and modelling of the Ge/sub x/Si/sub 1-x//Si BICFET
1992 / IEEE / 0-7803-0817-4
By: Iyer, S.S.; Croke, E.T.; Plummer, J.D.; Mierzwinski, M.E.; Harrell, M.J.;
A vertical submicron polysilicon thin-film transistor using a low temperature process
1994 / IEEE
By: Saraswat, K.C.; Min Cao; Tiemin Zhao; Plummer, J.D.;
Dispersion of MOS capacitance-voltage characteristics resulting from the random channel dopant ion distribution
1994 / IEEE
By: Plummer, J.D.; Watt, J.T.;
A novel floating gate spacer polysilicon TFT
1993 / IEEE / 0-7803-1450-6
By: Plummer, J.D.; Min Cao; Tiemin Zhao; Saraswat, K.C.;
Species, dose and energy dependence of implant induced transient enhanced diffusion
1993 / IEEE / 0-7803-1450-6
By: Huang, R.Y.S.; Lever, R.F.; Griffin, P.B.; Plummer, J.D.; Packan, P.A.; Kennel, H.W.;
Performance of the 3-D sidewall flash EPROM cell
1993 / IEEE / 0-7803-1450-6
By: Pein, H.B.; Plummer, J.D.;
Device implications of enhanced diffusion caused by the electrical deactivation of arsenic
1994 / IEEE / 0-7803-2111-1
By: Plummer, J.D.; Kuehne, S.C.; Griffin, P.B.; Rousseau, P.M.;
Study on hydrogenation of polysilicon thin film transistors by ion implantation
1995 / IEEE
By: Min Cao; Plummer, J.D.; Saraswat, K.C.; Tiemin Zhao;
Performance of the 3-D PENCIL flash EPROM cell and memory array
1995 / IEEE
By: Pein, H.; Plummer, J.D.;
Low threshold voltage quarter micron MOSFETs for low power applications
1995 / IEEE / 0-7803-3036-6
By: Zongjian Chen; Plummer, J.D.;
Enhanced diffusion by electrical deactivation of arsenic and its implications for bipolar devices
1996 / IEEE
By: Plummer, J.D.; Kuehne, S.C.; Griffin, P.B.; Rousseau, P.M.;
Optimization of quarter micron MOSFETs for low voltage/low power applications
1995 / IEEE / 0-7803-2700-4
By: Shott, J.; Burr, J.; Zongjian Chen; Plummer, J.D.;
The effect of source/drain processing on the reverse short channel effect of deep sub-micron bulk and SOI NMOSFETs
1995 / IEEE / 0-7803-2700-4
By: Scott, J.A.; Snyder, J.P.; Rousseau, P.M.; Crowder, S.W.; Plummer, J.D.; Griffin, P.B.;
High voltage LDMOS transistors in sub-micron SOI films
1996 / IEEE / 0-7803-3106-0
By: Paul, K.; Nguyen, C.T.; Huang, V.S.K.; Kuehne, S.C.; Wong, S.S.; Plummer, J.D.; Leung, Y.K.;
Investigation of body effect of fully depleted n channel SOI device as a function of body bias
1994 / IEEE / 0-7803-2406-4
By: Plummer, J.D.; Shott, J.; Ploeg, E.V.; Zongjian Chen;
A test structure advisor and a coupled, library-based test structure layout and testing environment
1996 / IEEE / 0-7803-2783-7
By: Plummer, J.D.; Kumar, M.V.; Lukaszek, W.;
A model for mobility degradation in highly doped arsenic layers
1996 / IEEE
By: Rousseau, P.M.; Plummer, J.D.; Luning, S.; Griffin, P.B.;
Vertical, fully-depleted, surrounding gate MOSFETs on sub-0.1 /spl mu/m thick silicon pillars
1996 / IEEE / 0-7803-3358-6
By: Plummer, J.D.; Auth, C.P.;
High voltage, high speed lateral IGBT in thin SOI for power IC
1996 / IEEE / 0-7803-3315-2
By: Kuehne, S.C.; Leung, Y.K.; Wong, S.S.; Plummer, J.D.; Paul, A.K.; Nguyen, C.T.; Huang, V.S.K.;
Arsenic deactivation enhanced diffusion and the reverse short-channel effect
1997 / IEEE
By: Griffin, P.B.; Crowder, S.W.; Rousseau, P.M.; Plummer, J.D.;
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
1997 / IEEE
By: Plummer, J.D.; Auth, C.P.;
Spatial temperature profiles due to nonuniform self-heating in LDMOS's in thin SOI
1997 / IEEE
By: Plummer, J.D.; Paul, A.K.; Nguyen, C.T.; Huang, V.S.K.; Kuehne, S.C.; Ying-Keung Leung; Wong, S.S.;
0.18 um dual Vt MOSFET process and energy-delay measurement
1996 / IEEE / 0-7803-3393-4
By: Zhongjian Chen; Greene, W.; Min Cao; Plummer, J.D.; Diaz, C.;
Applied bias slewing in transient Wigner function simulation of resonant tunneling diodes
1997 / IEEE
By: Biegel, B.A.; Plummer, J.D.;
CMOS technology scaling for low voltage low power applications
1994 / IEEE / 0-7803-1953-2
By: Zongjian Chen; Plummer, J.D.; Burr, J.; Shott, J.;
A trench-gate LIGBT structure and two LMCT structures in SOI substrates
1994 / IEEE / 0-7803-1494-8
By: Plummer, J.D.; Pein, H.B.; Disney, D.R.;
Design and characterization of SiGe TFT devices and process using Stanford's test chip design environment
1997 / IEEE / 0-7803-3243-1
By: Lukaszek, W.; Plummer, J.D.; Saraswat, K.C.; Subramanian, V.; Kumar, M.V.;
Nitrogen-doped poly spacer local oxidation
1997 / IEEE
By: Griffin, P.B.; Huang, S.-F.; Plummer, J.D.; Rissman, P.;
A test structure advisor and a coupled, library-based test structure layout and testing environment
1997 / IEEE
By: Plummer, J.D.; Lukaszek, W.; Kumar, M.V.;
Modeling stress effects on thin oxide growth kinetics
1997 / IEEE / 0-7803-3775-1
By: Plummer, J.D.; Griffin, P.B.; Huang, S.-F.; Rissman, P.;
Heating mechanisms of LDMOS and LIGBT in ultrathin SOI
1997 / IEEE
By: Goodson, K.E.; Paul, A.K.; Ying-Keung Leung; Wong, S.S.; Plummer, J.D.;
Thermal Oxidation Kinetics and Locos Isolation in Soi Materials
1992 / IEEE / 0-7803-0776-3
By: Plummer, J.D.; Griffin, P.; Crowder, S.;
A novel pillar DRAM cell for 4 Gbit and beyond
1998 / IEEE / 0-7803-4770-6
By: Hyun-Jin Cho; Plummer, J.D.; Griffin, P.B.; Nemati, F.;
A novel high density, low voltage SRAM cell with a vertical NDR device
1998 / IEEE / 0-7803-4770-6
By: Nemati, F.; Plummer, J.D.;
Localized intermixing of AlAs and GaAs layers for lithographic control of the lateral oxidation of AlAs
1998 / IEEE / 0-7503-0556-8
By: Massengale, A.R.; Harris, J.S., Jr.; Plummer, J.D.; Deal, M.D.; Tai, C.Y.;
Solid Modeling-based Parametric Operations For Device Design
1993 / IEEE / 0-7803-1338-0
By: Wong, W.T.; Plummer, J.D.; Dutton, R.W.; Yang, D.X.;
Lateral IGBT in thin SOI for high voltage, high speed power IC
1998 / IEEE
By: Wong, S.S.; Plummer, J.D.; Paul, A.K.; Ying-Keung Leung;
A simple model for threshold voltage of surrounding-gate MOSFET's
1998 / IEEE
By: Plummer, J.D.; Auth, C.P.;
Validation of two-dimensional implant and diffusion profiles using novel scanning capacitance microscope sample preparation and deconvolution techniques
1998 / IEEE / 0-7803-4774-9
By: Yu, G.M.; Plummer, J.D.; Griffin, P.B.;
Characterization of arsenic dose loss at the Si/SiO/sub 2/ interface using high resolution X-ray photoelectron spectrometry
1998 / IEEE / 0-7803-4774-9
By: Pianetta, P.; Kasnavi, R.; Plummer, J.D.; Griffin, P.B.; Renee Mo; Yun Sun;
Programmable Factory For Adaptable IC Manufacturing
1993 / IEEE
By: Saraswat, K.C.; Wood, S.C.; Plummer, J.D.; Losleben, P.;
Challenges for predictive process simulation in sub 0.1/spl mu/ silicon devices
1994 / IEEE
By: Plummer, J.D.;
High performance fully and partially depleted poly-Si surrounding gate transistors
1999 / IEEE / 4-930813-93-X
By: Hyun-Jin Cho; Plummer, J.D.;
A self-aligned split-gate flash EEPROM cell with 3-D pillar structure
1999 / IEEE / 4-930813-93-X
By: Plummer, J.D.; Hayashi, F.;
A novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memories
1999 / IEEE / 0-7803-5410-9
By: Nemati, F.; Plummer, J.D.;
SiGe heterojunctions in epitaxial vertical surrounding-gate MOSFETs
2000 / IEEE / 0-7803-6305-1
By: Plummer, J.D.; Date, C.K.;
Ultra low energy arsenic implant limits on sheet resistance and junction depth
2000 / IEEE / 0-7803-6305-1
By: Kasnavi, R.; Plummer, J.D.; Griffin, P.B.;
Kinetics of boron activation
2000 / IEEE / 0-7803-6279-9
By: Plummer, J.D.; Griffin, P.B.; Mokhberi, A.;
Silicon MOSFETs (conventional and non-traditional) at the scaling limit
2000 / IEEE / 0-7803-6472-4
By: Plummer, J.D.;
Modeling and fabrication of vertical pillar MOSFETs made in recrystallized Si
2000 / IEEE / 0-7803-6389-2
By: Plummer, J.D.; Hyun-Jin Cho;
50 nm Vertical Replacement-Gate (VRG) pMOSFETs
2000 / IEEE / 0-7803-6438-4
By: Sang-Hyun Oh; Hergenrother, J.M.; Plummer, J.D.; Wilk, G.D.; Weber, G.R.; Timko, A.G.; Sorsch, T.W.; Short, K.; Rosamilia, J.M.; Rafferty, C.S.; Morris, M.D.; Miner, J.F.; Lee, J.T.-C.; Kleiman, R.N.; King, C.A.; Keller, R.C.; Johnson, R.W.; Hillenius, S.J.; Green, M.L.; Grazul, J.L.; Gossmann, H.J.; Nigam, T.; Monroe, D.; Klemens, F.P.; Kornblit, A.; Mansfield, W.M.; Baker, M.R.; Barr, D.L.; Baumann, F.H.; Bolan, K.J.; Boone, T.; Ciampa, N.A.; Cirelli, R.A.; Eaglesham, D.J.; Ferry, E.J.; Fiory, A.T.; Frackoviak, J.; Garno, J.P.;
Material and process limits in silicon VLSI technology
2001 / IEEE
By: Plummer, J.D.; Griffin, P.B.;
Suppression of the floating-body effect using SiGe layers in vertical surrounding-gate MOSFETs
2001 / IEEE
By: Date, C.K.; Plummer, J.D.;
Increased hot-carrier effects using SiGe layers in vertical surrounding-gate MOSFETs
2001 / IEEE
By: Plummer, J.D.; Date, C.K.;
A 3-D sidewall flash EPROM cell and memory array
1993 / IEEE
By: Plummer, J.D.; Pein, H.;
A comparative study of dopant activation in boron, BF/sub 2/, arsenic, and phosphorus implanted silicon
2002 / IEEE
By: Elliott, K.; McCoy, S.; Paton, E.; Plummer, J.D.; Griffin, P.B.; Mokhberi, A.;
Integrated Electronics for a Reading Aid for the Blind
1969 / IEEE
By: Brugler, J.S.; Young, W.T.; Salsbury, P.J.; Plummer, J.D.; Meindl, J.D.;
MOS electronics for a portable reading aid for the blind
1972 / IEEE
By: Plummer, J.D.; Meindl, J.D.;
A monolithic 200-V CMOS analog switch
1976 / IEEE
By: Plummer, J.D.; Meindl, J.D.;
Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces
1980 / IEEE
By: Sun, S.C.; Plummer, J.D.;
Impact of lateral source/drain abruptness on device performance
2002 / IEEE
By: Griffin, P.; Kasnavi, R.; Kwong, M.Y.; Dutton, R.W.; Plummer, J.D.;
I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q
2002 / IEEE / 0-7803-7462-2
By: Gopalakrishnan, K.; Plummer, J.D.; Griffin, P.B.;
A physics based approach to ultra-shallow p/sup +/-junction formation at the 32 nm node
2002 / IEEE / 0-7803-7462-2
By: Gelpey, J.; Elliott, K.; Ross, J.; McCoy, S.; Paton, E.; Barbolla, J.; Griffin, P.B.; Aboy, M.; Pelaz, L.; Mokhberi, A.; Marques, L.; Plummer, J.D.;
Atomistic modeling of B activation and deactivation for ultra-shallow junction formation
2003 / IEEE / 0-7803-7826-1
By: Barbolla, J.; Aboy, M.; Marques, L.A.; Pelaz, L.; Mokhberi, A.; Plummer, J.D.; Griffin, P.B.; Takamura, Y.;

Next Page
Return To Top