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Author: Pacha, C.

Results

Application of terminal dynamics in cellular neural networks
1996 / IEEE / 0-8186-7373-7
By: Goser, K.; Pacha, C.;
Aspects of systems and circuits for nanoelectronics
1997 / IEEE
By: Pacha, C.; Goser, K.F.; Rossmann, M.L.; Kanstein, A.;
InP-based HFETs and RTDs for high speed digital circuitry
1998 / IEEE / 0-7803-4900-8
By: Bertenburg, R.M.; Janssen, G.; Brennemann, A.; Pacha, C.; Auer, U.; Brockerhoff, W.; Tegude, F.-J.; Prost, W.; Goser, K.F.; Bushehri, E.;
Resonant tunneling transistors for threshold logic circuit applications
1999 / IEEE / 0-7695-0104-4
By: Auer, U.; Goser, K.; Glosekjtter, P.; Pacha, C.; Tegude, E.; Prost, W.;
Associative matrix for nano-scale integrated circuits
1999 / IEEE / 0-7695-0043-9
By: Glosekotter, P.; Pacha, C.; Goser, K.;
Digital circuit design based on the resonant-tunneling-hetero-junction-bipolar-transistor
2000 / IEEE / 0-7695-0843-X
By: Pacha, C.; Glosekotter, P.; Velling, P.; Tegude, F.J.; Goser, K.F.; Agethen, M.; Auer, U.; Prost, W.; Wirth, G.I.;
Threshold logic circuit design of parallel adders using resonant tunneling devices
2000 / IEEE
By: Pacha, C.; Goser, K.F.; Tegude, F.-J.; Prost, W.; Auer, U.; Brennemann, A.; Glosekotter, P.; Burwick, C.;
Tunnelling diode technology
2001 / IEEE / 0-7695-1083-3
By: Prost, W.; Schmidt, O.G.; Eberl, K.; Duschl, R.; Auer, U.; Goser, K.F.; Pacha, C.; Tegude, F.-J.;
Technology of a depth-2 full-adder circuit using the InP RTD/HFET MOBILE
2001 / IEEE / 0-7803-6700-6
By: Degenhardt, J.; Auer, U.; Prost, W.; Tegude, F.-J.; Goser, K.F.; Pacha, C.; Brennemann, A.;
Impact of technology parameters on inverter delay of UTB-SOI CMOS
2002 / IEEE / 0-7803-7439-8
By: Pacha, C.; Schulz, T.; Risch, L.;
Experimental threshold logic implementations based on resonant tunnelling diodes
2002 / IEEE / 0-7803-7596-3
By: Kim, S.O.; Prost, W.; Tegude, F.-J.; Goser, K.F.; Reimann, T.; van Husen, H.; Pacha, C.; Glosekotter, P.;
Asynchronous circuit design based on the RTBT monostable-bistable logic transition element (MOBILE)
2002 / IEEE / 0-7695-1807-9
By: Tegude, F.J.; Reimann, T.; van Husen, H.; Kim, S.; Glosekotter, P.; Prost, W.; Goser, K.F.; Pacha, C.;
Polymer gate dielectric pentacene TFTs and circuits on flexible substrates
2002 / IEEE / 0-7803-7462-2
By: Radlik, W.; Schmid, G.; Zschieschang, U.; Halik, M.; Klauk, H.; Brederlow, R.; Thewes, R.; Weber, W.; Pacha, C.; Briole, S.;
Evaluation of the performance potential of organic TFT circuits
2003 / IEEE / 0-7803-7707-9
By: Pacha, C.; Gorriz-Saez, J.-M.; Schmid, G.; Halik, M.; Zschieschang, U.; Thewes, R.; Klauk, H.; Briole, S.; Brederlow, R.; Weber, W.;
AC-only RF ID tags for barcode replacement
2004 / IEEE / 0-7803-8267-6
By: Kaiser, A.; Goser, K.; Pacha, C.; Briole, S.; Brederlow, R.; Weber, W.; Thewes, R.;
Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS
2004 / IEEE / 0-7803-8478-4
By: Martin, B.; Pacha, C.; Thewes, R.; Berthold, J.; Seegebrecht, P.; Schmitt-Landsiedel, D.; Brederlow, R.; von Arnim, K.;
Efficiency of body biasing in 90 nm CMOS for low power digital circuits
2004 / IEEE / 0-7803-8480-6
By: Thewes, R.; Brederlow, R.; Fiedler, H.; Seegebrecht, P.; Berthold, J.; von Arnim, K.; Borinski, E.; Pacha, C.;
The tunneling field effect transistor (TFET) used in a single-event-upset (SEU) insensitive 6 transistor SRAM cell in ultra-low voltage applications
2004 / IEEE / 0-7803-8536-5
By: Schmitt-Landsiedel, D.; Georgakos, G.; Hansch, W.; Peng-Fei Wang; Pacha, C.; Henzler, S.; Nirschl, T.;
The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes
2004 / IEEE / 0-7803-8684-1
By: Kakoschke, R.; Schrufer, K.; Heinrich, R.; Sedlmeir, J.; Weber, C.; Wang, P.-F.; Nirschl, Th.; Schmitt-Landsiedel, D.; Hansch, W.; Ruderer, E.; Georgakos, G.; Olbrich, A.; Ostermayr, M.; Schulz, T.; Pacha, C.; Holz, J.;
Efficiency of body biasing in 90-nm CMOS for low-power digital circuits
2005 / IEEE
By: Thewes, R.; Brederlow, R.; Seegebrecht, P.; Fiedler, H.; Berthold, J.; Borinski, E.; von Arnim, K.; Pacha, C.;
System and circuit aspects of nanoelectronics
1998 / IEEE
By: Pacha, C.; Goser, K.;
A threshold logic full adder based on resonant tunneling transistors
1998 / IEEE
By: Pacha, C.; Prost, W.; Brennemann, A.; Goser, K.;
A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies
2005 / IEEE / 0-7803-8904-2
By: Thewes, R.; Seegebrecht, P.; von Arnim, K.; Pacha, C.;
Pseudo Dynamic Gate Design Based on the Resonant Tunneling-Bipolar Transistor (RTBT)
2002 / IEEE / 88-900847-8-2
By: Reimann, T.; Gloesekoetter, P.; Goser, K.F.; Tegude, F.J.; Pacha, C.; van Husen, H.; Kim, S.; Prost, W.;
Dynamic state-retention flip flop for fine-grained sleep-transistor scheme
2005 / IEEE / 0-7803-9205-1
By: Fischer, T.; Eireiner, M.; Fischer, J.; Fulde, M.; Spindler, P.; Teichmann, P.; Georgakos, G.; Pacha, C.; Nirschi, T.; Henzler, S.; Schmitt-Landsiedel, D.; Berthold, J.;
FinFET current mirror design and evaluation
2005 / IEEE / 0-7803-9515-8
By: Duvvury, C.; Gossner, H.; Cleavelin, R.; Campise, M.; Kulkarni, M.; Marshall, A.; Xiong, W.; Wilks, B.; VonArnim, K.; Schulz, T.; Schruefer, K.; Russ, C.; Pacha, C.; Knoblinger, G.; Gostkowski, M.;
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead
2006 / IEEE
By: Berthold, J.; Pacha, C.; Nirschl, T.; Eireiner, M.; Georgakos, G.; Henzler, S.; Schmitt-Landsiedel, D.;
A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions
2006 / IEEE / 1-4244-0079-1
By: Homke, O.; Beshenar, J.; Sauzon, G.; Georgakos, G.; Pacha, C.; Berthold, J.; Luftner, T.; Sauer, M.; Juhoor, G.; Mabrouki, H.; Acharya, P.; Knight, R.; Klein, A.; Yakovleff, A.; Schmitt-Landsiedel, D.; Henzler, S.; Hober, P.; Just, K.; Mahrla, P.;
Circuit design issues in multi-gate FET CMOS technologies
2006 / IEEE / 1-4244-0079-1
By: Berthold, J.; Russ, C.; Marshall, A.; Knoblinger, G.; Nirschl, T.; Gostkowski, M.; Weize Xiong; Schulz, T.; von Arnim, K.; Pacha, C.; Schruefer, K.; Cleavelin, R.; Patruno, P.; Duvvury, C.; Gossner, H.;
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions
2007 / IEEE
By: Pacha, C.; Georgakos, G.; Lueftner, T.; Sauer, M.; Buch, S.; Bonnardot, A.; Acharya, P.; Knight, R.J.; Klein, A.; Yakovleff, A.; Berthold, J.; Schmitt-Landsiedel, D.; Henzler, S.; Hober, P.; Just, K.; Mahrla, P.; Beshenar, J.; Hoemke, O.; Sauzon, G.;
Effects of Temperature on Metal Gate FinFET Circuit Performance
2006 / IEEE / 1-4244-0289-1
By: Marshall, A.; Patruno, P.; Schruefer, K.; Schulz, T.; Cleavelin, C.R.; Weize Xiong; Pacha, C.; Konblinger, G.; Matthews, K.; Von Armin, K.;
Multi-Gate MOSFET Design
2006 / IEEE / 1-4244-0302-2
By: Russ, C.; Haibach, P.; Marshall, A.; Kuttner, F.; Pacha, C.; Knoblinger, G.; Schruefer, K.; Cleavelin, C.R.; Xiong, W.; Bertolissi, L.; Engelstaedter, J.P.; Arnim, K.V.; Schulz, T.; Patruno, P.;
Statistical Characterization of Hold Time Violations in 130nm CMOS Technology
2006 / IEEE / 1-4244-0302-2
By: Reis, R.; Kastensmidt, F.; Neuberger, G.; Pacha, C.; Brederlow, R.; Wirth, G.;
Multi-Gate MOSFET Design
2006 / IEEE / 1-4244-0301-4
By: Schulz, T.; Arnim, K.V.; Haibach, P.; Patruno, P.; Russ, C.; Marshall, A.; Kuttner, F.; Pacha, C.; Knoblinger, G.; Schruefer, K.; Cleavelin, C.R.; Xiong, W.; Bertolissi, L.; Engelstaedter, J.P.;
Ring Oscillator Performance and Parasitic Extraction Simulation in Finfet Technology
2006 / IEEE / 1-4244-0669-2
By: Rinn Cleavelin, C.; Marshall, A.; Kulkarni, M.; Patruno, P.; Weize Xiong; Schruefer, K.; Schulz, T.; von Armin, K.; Pacha, C.;
Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies
2007 / IEEE / 1-4244-0584-X
By: Xiong, W.; Schulz, T.; Cleavelin, C.R.; Berthold, J.; Patruno, P.; von Arnim, K.; Schruefer, K.; Pacha, C.;
Evaluation of FinFET RF Building Blocks
2007 / IEEE / 978-1-4244-0879-5
By: Baumann, U.; Pacha, C.; Schulz, T.; Siprak, D.; Von Arnim, K.; Hodel, U.; Marshall, A.; Fulde, M.; Knoblinger, G.; Schruefer, K.; Patruno, P.; Cleavelin, C.R.; Xiong, W.;
An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits
2007 / IEEE / 978-1-4244-1507-6
By: Pacha, C.; von Arnim, K.; Berthold, J.; Schriifer, K.; Schulz, T.; Hofmann, K.;
Leakage Reduction in Sub-100nm CMOS Technologies: Bridging the Gap Between Technology, Circuit Design and Low Power Product Requirements
2007 / IEEE / 978-1-4244-1507-6
By: Berthold, J.; Pacha, C.;
Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits
2007 / IEEE / 978-1-4244-1125-2
By: Cleavelin, C.-R.; Baumann, T.; Marshall, A.; San, K.T.; Xiong, W.; Schruefer, K.; Schulz, T.; Bauer, F.; von Arnim, K.; Pacha, C.; Berthold, J.;
Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement
2007 / IEEE / 978-1-4244-1125-2
By: Pacha, C.; Schmitt-Landsiedel, D.; Dienstuhl, J.; Schoenauer, T.; Niedermeier, T.; Berthold, J.; Baumann, T.;
Layout options for stability tuning of SRAM cells in multi-gate-FET technologies
2007 / IEEE / 978-1-4244-1125-2
By: Fulde, M.; Schulz, T.; Schmitt-Landsiedel, D.; Pacha, C.; von Arnim, K.; Bauer, F.; Nackaerts, A.; Georgakos, G.; Schrufer, K.; Cleavelin, C.-R.; San, K.T.; Xiong, W.; Jurczak, M.;
Silicon on Insulator - The Perfect Material for Implantable Electronics?
2007 / IEEE / 978-1-4244-1626-4
By: Schulz, T.; Von Arnim, K.; Russ, C.; Weize Xiong; Pacha, C.; Schruefer, K.; Cleavelin, C.R.; Marshall, A.; Patruno, P.; Knoblinger, G.;
Advances in Multi-Gate MOSFET Circuit Design
2007 / IEEE / 978-1-4244-1377-5
By: Xiong, W.; Siprak, D.; Russ, C.; Arnim, K.v.; Bauer, F.; Pacha, C.; Marshall, A.; Fulde, M.; Knoblinger, G.; Schmitt-Landsiedel, D.; Schruefer, K.; Cleavelin, C.R.;
High-�/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
2009 / IEEE / 978-1-4244-2784-0
By: Park, D.-G.; Stein, K.; Khare, M.; Divakaruni, R.; Steegen, A.; Lindsay, R.; Sherony, M.; Narayanan, V.; Samavedam, S.; Theon, V.-Y.; Chudzik, M.; Schepis, D.; Haetty, J.; Chowdhury, M.; Kanarsky, T.; Yan, W.; Chen, J.; Zhuang, H.; Jaeger, D.; Chen, X.; Loesing, R.; Tang, T.; Hatzistergos, M.; Moumen, N.; von Arnim, K.; Han, S.; Schruefer, K.; Lee, Y.; Han, J.-P.; Li, W.; Yin, H.; Pacha, C.; Kim, N.; Ostermayr, M.; Eller, M.; Kim, S.; Kim, K.;
Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors
2009 / IEEE / 978-1-6055-8497-3
By: Pacha, C.; Schmitt-Landsiedel, D.; Baumann, T.;
A voltage scaling model for performance evaluation in digital CMOS circuits
2009 / IEEE / 978-1-4244-5641-3
By: Schruefer, K.; von Arnim, K.; Berthold, J.; Pacha, C.; Schulz, T.; Hofmann, K.; Baumann, T.;
Highly accurate product-level aging monitoring in 40nm CMOS
2010 / IEEE / 978-1-4244-5450-1
By: Hatsch, J.; Reisinger, H.; Hofmann, K.; Pacha, C.; Baumann, T.; Kodytek, T.; Ermisch, K.; Arnim, K.v.; Georgakos, G.; Pompl, T.; Gustin, W.; Schlunder, C.;

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