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Author: Ott, J.A.

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A 0.021 �m2 trigate SRAM cell with aggressively scaled gate and contact pitch
2011 / IEEE / 978-1-4244-9949-6
By: Guillorn, M.A.; Chang, J.; Haensch, W.; Fuller, N.; Narayanan, V.; Sikorski, E.; Graham, W.; To, B.; Bucchignano, J.; Klaus, D.P.; Kratschmer, E.; Newbury, J.; Zhang, Z.; Lavoie, C.; Lauer, I.; Mauer, S.; Khater, M.; Bangsaruntip, S.; Brink, M.; Liu, F.; Majumdar, A.; Ott, J.A.; Bruce, R.; Pyzyna, A.; Engelmann, S.; Glodde, M.; Joseph, E.;
Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node
2011 / IEEE / 978-1-4244-9949-6
By: Guillorn, M.; Chang, J.B.; Haensch, W.E.; Ott, J.A.; Solomon, P.M.; Pyzyna, A.; Engelmann, S.U.; Lin, C.-H.;
High performance 0.25 mu m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation
1991 / IEEE / 0-7803-0243-5
By: Ott, J.A.; Iyer, S.S.; Aitken, J.M.; Tejwani, M.J.; Restle, P.J.; Subbana, S.; Kesan, V.P.;
Hole confinement and its impact on low-frequency noise in SiGe pFETs on sapphire
1997 / IEEE / 0-7803-4100-7
By: Dubbelday, W.B.; Niu, G.; Ott, J.A.; Chu, J.O.; Mooney, P.M.; Kavanagh, K.L.; Meyerson, B.S.; Lagnado, I.; Cressler, J.D.; Mathew, S.J.;
Hole confinement and low-frequency noise in SiGe pFETs on silicon-on-sapphire
1999 / IEEE
By: Kavanagh, K.L.; Guofu Niu; Mathew, S.J.; Lagnado, I.; Meyerson, B.S.; Dubbelday, W.B.; Mooney, P.M.; Chu, J.O.; Ott, J.A.; Cressler, J.D.;
High-performance SiGe pMODFETs grown by UHV-CVD
1999 / IEEE / 0-7803-5298-X
By: Chu, J.O.; Hammond, R.; Koester, S.J.; Jenkins, K.A.; Perraud, L.; Mooney, P.M.; Ott, J.A.;
Silicon-on-sapphire for RF Si systems 2000
2000 / IEEE / 0-7803-6255-1
By: Ott, J.A.; Chu, J.O.; Hammond, R.; Koester, S.J.; Dubbelday, W.B.; Mooney, P.M.; Lagnado, I.; de la Houssaye, P.R.; Jenkins, K.A.; Perraud, L.;
Low-noise SiGe pMODFETs on sapphire with 116 GHz f/sub max/
2000 / IEEE / 0-7803-6472-4
By: Chu, J.O.; Hammond, R.; Koester, S.J.; De la Houssaye, P.R.; Lagnado, I.; Webster, C.S.; Ott, J.A.; Mooney, P.M.;
RF systems based on silicon-on-sapphire technology
2000 / IEEE / 0-7803-6389-2
By: Lagnado, I.; De la Houssaye, P.R.; Dubbelday, W.B.; Koester, S.J.; Jenkins, K.A.; Chu, J.O.; Ott, J.A.; Mooney, P.M.; Perraud, L.; Hammond, R.;
SiGe pMODFETs on silicon-on-sapphire substrates with 116 GHz f/sub max/
2001 / IEEE
By: Perraud, L.; de la Houssaye, P.R.; Lagnado, I.; Webster, C.S.; Jenkins, K.A.; Koester, S.J.; Ott, J.A.; Mooney, P.M.; Chu, J.O.; Hammond, R.;
Fabrication of a novel vertical pMOSFET with enhanced drive current and reduced short-channel effects and floating body effects
2001 / IEEE / 4-89114-012-7
By: Banerjee, S.K.; Register, L.F.; Tasch, A.F.; Xiangdong Chen; Qiqing Ouyang; Ott, J.A.; Chu, J.O.;
High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric
2002 / IEEE / 0-7803-7462-2
By: Kozlowski, P.M.; Ott, J.A.; Copel, M.; Chan, K.K.; Okorn-Schmidt, H.; Steen, S.E.; Haensch, W.E.; Jones, E.C.; Huiling Shang; Wong, H.-S.P.; Cordes, S.A.;
Implications of gate design on RF performance of sub-100 nm strained-Si/SiGe nMODFETs
2003 / IEEE / 0-7803-7826-1
By: Saenger, K.L.; Chu, J.O.; Koester, S.J.; Ouyang, Q.; Jenkins, K.A.; Ott, J.A.;
On the integration of CMOS with hybrid crystal orientations
2004 / IEEE / 0-7803-8289-7
By: Boyd, D.C.; Ott, J.A.; Sung, C.Y.; Zhu, H.; Bernstein, K.; Fried, D.M.; Chudzik, M.P.; Steen, S.E.; Holt, J.R.; To, B.N.; Zhang, Y.; Oldiges, P.; Jamin, F.F.; Surpris, Y.; Lehner, E.A.; Yang, H.S.; Mo, R.T.; Murthy, C.S.; Chan, K.K.; Shi, L.; Ieong, M.; Ku, S.H.; Chan, V.; Yang, M.; Rovedo, N.;
Laterally-scaled Si/SiGe n-MODFETs with in situ and ion-implanted p-well doping
2004 / IEEE / 0-7803-8284-6
By: Jahnes, C.V.; Saenger, K.L.; Koester, S.J.; Steen, S.E.; Chu, J.O.; Tornello, J.A.; Canaperi, D.F.; Ott, J.A.; Ouyang, Q.C.;
Threshold voltage control in NiSi-gated MOSFETs through SIIS
2005 / IEEE
By: Kedzierski, J.; Meikei Ieong; Ott, J.A.; Kozlowski, P.M.; Boyd, D.; Ronsheim, P.; Cabral, C., Jr.; Zafar, S.;
300 mm SGOI/strain-Si for high-performance CMOS
2004 / IEEE / 0-7803-8497-0
By: Bedell, S.W.; Reznicek, A.; Sadana, D.K.; Mitchell, R.; Ott, J.A.; Fogel, K.E.; Hovel, H.J.;
Laterally scaled Si-Si/sub 0.7/Ge/sub 0.3/ n-MODFETs with f/sub max/>200 GHz and low operating bias
2005 / IEEE
By: Jahnes, C.V.; Tornello, J.A.; Canaperi, D.F.; Jenkins, K.A.; Ott, J.A.; Steen, S.E.; Chu, J.O.; Saenger, K.L.; Koester, S.J.; Ouyang, Q.C.;
Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS
2004 / IEEE / 0-7803-8684-1
By: Jamison, P.; Gusev, E.P.; Bedell, S.; Chu, J.O.; Huiling Shang; Ying Zhang; Guarini, K.W.; Meikei Ieong; Sadana, D.; Copel, M.; Ott, J.A.;
Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond
2004 / IEEE / 0-7803-8684-1
By: Fried, D.M.; Guarini, K.W.; Hergenrother, J.M.; Topol, A.W.; Chang, L.; Sekaric, L.; Sleight, J.W.; McNab, S.J.; Newbury, J.; Steen, S.E.; Gibson, G.; Zhang, Y.; Fuller, N.C.M.; Bucchignano, J.; Lavoie, C.; Cabral Jr, C.; Canaperi, D.; Dokumaci, O.; Frank, D.J.; Duch, E.A.; Babich, I.; Wong, K.; Ott, J.A.; Adams, C.D.; Dalton, T.J.; Nunes, R.; Medeiros, D.R.; Viswanathan, R.; Ketchen, M.; Ieong, M.; Haensch, W.;
Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates
2005 / IEEE / 4-900784-00-1
By: Klymko, N.; Wildman, H.; Rovedo, N.; Fischetti, M.; Jinghong Li; Utomo, H.; Huajie Chen; Panda, S.; Holt, J.; Min Yang; Qiqing Ouyang; Chun-Yung Sung; Meikei Ieong; Ott, J.A.; Bryant, A.; Fried, D.M.; Costrini, G.; Kanarsky, T.;
Characteristics of high performance PFETs with embedded SiGe source/drain and <100> channels on 45/spl deg/ rotated wafers
2005 / IEEE / 0-7803-9058-X
By: Rim, K.; Boyd, D.; Panda, S.; Fischetti, M.; Meikei Ieong; Qiqing Ouyang; Ott, J.A.;
Improved DC and RF performance in Si/SiGe n-MODFETs with ion-implanted buried p-well doping
2005 / IEEE
By: Ott, J.A.; Saenger, K.L.; Ouyang, Q.C.; Chu, J.O.; Canaperi, D.F.; Koester, S.J.; Jahnes, C.V.; Tornello, J.A.;
Development of stacking faults in strained silicon layers
2005 / IEEE / 0-7803-9212-4
By: Fogel, K.; Ott, J.A.; Hovel, H.J.; Yang, B.; Domenicucci, A.G.; Bedell, S.W.; Reznicek, A.; Sadana, D.K.;
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
2005 / IEEE / 0-7803-9212-4
By: Chidambarrao, D.; Venigalla, R.; Dokumaci, O.; Black, L.; Nayfeh, H.; Ren, Z.; Sleight, J.W.; Hergenrother, J.M.; Singh, D.V.; Haensch, W.; Ieong, M.; Guarini, K.W.; Khare, M.; Ott, J.A.; Nomura, A.; Tessier, B.L.; Pan, J.;
High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates
2005 / IEEE / 0-7803-9268-X
By: Saenger, K.L.; Pfeiffer, G.; Ng, H.Y.; Haizhou Yin; Chun-Yung Sung; Wann, C.H.; Zhibin Ren; Rong Zhang; de Souza, J.P.; Sadana, D.; Rovedo, N.; Raccioppo, M.; Chan, V.; Nguyen, P.Y.; Mo, R.T.; Madan, A.; Zhijiong Luo; Lee, H.K.; Ku, V.; Kempisty, J.J.; Bendernagel, R.; Ott, J.A.; Jinghong Li; Crowder, S.W.;
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
2005 / IEEE / 0-7803-9268-X
By: Hergenrother, J.M.; Natzle, W.; Sleight, J.W.; Singh, D.V.; Haensch, W.; Ieong, M.; Ott, J.A.; Nomura, A.; Tessier, B.L.; Ren, Z.; Pan, J.; Venigalla, R.; Chidambarrao, D.; Nakayama, H.; Chang, J.B.; Black, L.; Dokumaci, O.; Jenkins, K.A.;
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
2006 / IEEE
By: Sleight, J.W.; Ren, Z.; Singh, D.V.; Nayfeh, H.M.; Haensch, W.; Ieong, M.; Guarini, K.W.; Khare, M.; Ott, J.A.; Tessier, B.L.; Hergenrother, J.M.; Natzle, W.; Pan, J.; Venigalla, R.; Chidambarrao, D.; Black, L.; Dokumaci, O.;
Hybrid-orientation technology (HOT): opportunities and challenges
2006 / IEEE
By: Min Yang; Meikei Ieong; Fischetti, M.V.; Burns, L.E.; Ott, J.A.; Chan, K.K.; Chan, V.W.C.; Chou, A.I.; Stathis, J.H.; Fried, D.M.; Shi, L.; Gusev, E.;
Silicon on Insulator CMOS with Hybrid Crystal Orientation Using Double Wafer Bonding
2006 / IEEE / 0-7803-9748-7
By: Chan, K.K.; Yang, M.; Ieong, M.; D'Emic, C.; Meyer, R.; Scerbo, C.; Newbury, J.; Canaperi, D.; Medd, S.; To, B.; Graham, W.; Sikorski, E.; Zhang, Y.; Shi, L.; Kumar, A.; Ott, J.A.; Patel, J.; Schultz, R.; Kry, H.;
GaAs MOS Capacitors and Self-Aligned MOSFETs with HfO2 Gate Dielectrics
2006 / IEEE / 0-7803-9748-7
By: Sousa, M.; Locquet, J.-P.; Fompeyrine, J.; Webb, D.J.; Sadana, D.K.; Ott, J.A.; Neumayer, D.A.; Yanning Sun; Kiewra, E.W.; Koester, S.J.; Germann, R.;
Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates
2006 / IEEE / 1-4244-0161-5
By: Ott, J.A.; de Souza, J.P.; Bedell, S.W.; Pfeiffer, G.; Bendernagel, R.; Chan, V.; Sadana, D.K.; Sung, C.Y.; Khare, M.; Ieong, M.; Shahidi, G.; Zhang, R.; Hovel, H.J.; Saenger, K.L.; Ren, Z.; Haizhou Yin;
Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS
2006 / IEEE / 1-4244-0438-X
By: Sung, C.Y.; Ng, H.; Haizhou Yin; Shahidi, G.; Khare, M.; Sadana, D.K.; Fogel, K.; Rovedo, N.; Luo, Z.J.; Ku, V.; Kelly, R.; Mesfin, A.; Cheng, K.; Liu, J.; Wang, G.; Chen, X.; Ren, Z.; Ko, S.B.; Bendernagel, R.; Pfeiffer, G.; Ott, J.A.; Li, J.; Zhang, R.; Crowder, S.; Chan, V.; Saenger, K.L.;
Scalability of Direct Silicon Bonded (DSB) Technology for 32nm Node and Beyond
2007 / IEEE / 978-4-900784-03-1
By: Haizhou Yin; Sung, C.Y.; Shahidi, G.; Khare, M.; Park, D.; Crowder, S.W.; Ishimaru, K.; Takayanagi, M.; Sadana, D.K.; Bendernagel, R.; Klemhenz, R.; Pfeiffer, G.; Fogel, K.; Rovedo, N.; Luo, Z.J.; Chen, X.; Ott, J.A.; Li, J.; Wallner, T.A.; Stein, K.J.; Zhang, R.; Ng, H.; Saenger, K.L.; Hamaguchr, M.; Hasumi, R.; Ohuchr, K.;
Effect of End-of-Range Defects on Device Leakage in Direct Silicon Bonded (DSB) Technology
2008 / IEEE / 978-1-4244-1614-1
By: Haizhou Yin; Shahidi, G.; Park, D.-G.; Ning, T.H.; Ishimaru, K.; Takayanagi, M.; Sadana, D.K.; Kleinhenz, R.; Pfeiffer, G.; Fogel, K.; Rovedo, N.; Luo, Z.J.; Chen, X.; Ott, J.A.; Cai, J.; Zhang, R.; Ohuchi, K.; Hasumi, R.; Sung, C.Y.; Saenger, K.L.; Hamaguchi, M.;
Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs
2008 / IEEE
By: Sadana, D.K.; Koester, S.J.; Fogel, K.; Arnold, J.; Ott, J.A.; Majumdar, A.; Bedell, S.W.;
Higher hole mobility induced by twisted Direct Silicon Bonding (DSB)
2008 / IEEE / 978-1-4244-1802-2
By: Hamaguchi, M.; Yin, H.; Ishimaru, K.; Shahidi, G.; Park, D.; Takayanagi, M.; Sadana, D.K.; de Souza, J.P.; Fogel, K.; Utomo, H.; Rovedo, N.; Zhang, R.; Ronsheim, P.; Zhu, Z.; Domenicucci, A.G.; Li, J.; Biscardi, M.; Kang, H.; Ott, J.A.; Takasu, Y.; Ohuchi, K.; Iijima, R.; Hasumi, R.; Sung, C.Y.; Saenger, K.L.;
DC and RF Characterization of Sub-100-nm-Gate-Length Strained Ge-on-Insulator p-MOSFETs
2008 / IEEE / 978-1-4244-1942-5
By: Majumdar, A.; Bedell, S.W.; Sadana, D.K.; Koester, S.J.; Fogel, K.; Arnold, J.; Ott, J.A.; Jenkins, K.A.;
High-$\kappa$/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length
2010 / IEEE
By: Khater, M.H.; Haensch, W.; Jin Cai; Lavoie, C.; D'Emic, C.; Qingyun Yang; Bin Yang; Guillorn, M.; Klaus, D.; Ott, J.A.; Yu Zhu; Ying Zhang; Changhwan Choi; Frank, M.M.; Kam-Leung Lee; Narayanan, V.; Dae-Gyu Park; Qiqing Ouyang; Zhen Zhang;

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