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Author: Narayanan, V.

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Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue)
2011 / IEEE
By: Roy, K.; Narayanan, V.; Macii, E.;
Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (First Issue)
2011 / IEEE
By: Roy, K.; Narayanan, V.; Macii, E.;
Development of a Heat Sink With Periodic Asymmetric Structures Using Grayscale Lithography and Deep Reactive Ion Etching
2012 / IEEE
By: Ellis, C.D.; Bhavnani, S.H.; Narayanan, V.; Kapsenberg, F.; Thiagarajan, N.;
Qualcomm Context-Awareness Symposium Sets Research Agenda for Context-Aware Smartphones
2012 / IEEE
By: McGuinness, D.L.; Albelson, H.; Narayanan, V.; Nanda, S.; Lukowicz, P.; Jordan, M.I.;
Automated mapping for reconfigurable single-electron transistor arrays
2011 / IEEE / 978-1-4503-0636-2
By: Datta, S.; Chun-Yao Wang; Eachempati, S.; Yung-Chih Chen; Narayanan, V.; Yuan Xie;
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08�m2 SRAM cell
2011 / IEEE / 978-1-61284-175-5
By: Cheng, K.; Khakifirooz, A.; Kulkarni, P.; Ponoth, S.; Haran, B.; Kumar, A.; Adam, T.; Reznicek, A.; Loubet, N.; He, H.; Kuss, J.; Wang, M.; Levin, T.M.; Monsieur, F.; Liu, Q.; Sreenivasan, R.; Cai, J.; Kimball, A.; Mehta, S.; Luning, S.; Zhu, Y.; Zhu, Z.; Yamamoto, T.; Bryant, A.; Lin, C.; Naczas, S.; Jagannathan, H.; Edge, L.F.; Allegret-Maret, S.; Dube, A.; Kanakasabapathy, S.; Schmitz, S.; Inada, A.; Seo, S.; Raymond, M.; Zhang, Z.; Yagishita, A.; Demarest, J.; Li, J.; Hopstaken, M.; Berliner, N.; Upham, A.; Johnson, R.; Holmes, S.; Standaert, T.; Smalley, M.; Zamdmer, N.; Ren, Z.; Wu, T.; Bu, H.; Paruchuri, V.; Sadana, D.; Narayanan, V.; Haensch, W.; O'Neill, J.; Hook, T.; Khare, M.; Doris, B.;
An algorithm-architecture co-design framework for gridding reconstruction using FPGAs
2011 / IEEE / 978-1-4503-0636-2
By: Kestur, S.; Irick, K.; Sungho Park; Al Maashri, A.; Narayanan, V.; Chakrabarti, C.;
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores
2011 / IEEE / 978-1-4503-0636-2
By: Mishra, A.; Saripalli, V.; Narayanan, V.; Datta, S.;
Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores
2011 / IEEE / 978-1-61284-660-6
By: Kultursay, E.; Swaminathan, K.; Datta, S.; Kandemir, M.; Narayanan, V.; Saripalli, V.;
Full metal gate with borderless contact for 14 nm and beyond
2011 / IEEE / 978-1-4244-9949-6
By: Seo, S.; Edge, L.F.; Paruchuri, V.K.; Narayanan, V.; Khare, M.; Divakaruni, R.; Doris, B.; Stathis, J.H.; Park, D.; Cartier, E.A.; Chang, J.; Brown, S.L.; Hopstaken, M.; Bruley, J.; Haran, B.; Vo, T.; Li, J.T.; Horak, D.; Fan, S.; Sankarapandian, M.; Ariyoshi, K.; Jamison, P.; Watanabe, K.; Wang, M.M.; Adam, L.; Inada, A.; Frank, M.; Kanakasabapathy, S.;
A 0.021 �m2 trigate SRAM cell with aggressively scaled gate and contact pitch
2011 / IEEE / 978-1-4244-9949-6
By: Guillorn, M.A.; Chang, J.; Haensch, W.; Fuller, N.; Narayanan, V.; Sikorski, E.; Graham, W.; To, B.; Bucchignano, J.; Klaus, D.P.; Kratschmer, E.; Newbury, J.; Zhang, Z.; Lavoie, C.; Lauer, I.; Mauer, S.; Khater, M.; Bangsaruntip, S.; Brink, M.; Liu, F.; Majumdar, A.; Ott, J.A.; Bruce, R.; Pyzyna, A.; Engelmann, S.; Glodde, M.; Joseph, E.;
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08�m2 SRAM cell
2011 / IEEE / 978-1-4244-9949-6
By: Cheng, K.; Khakifirooz, A.; Kulkarni, P.; Ponoth, S.; Haran, B.; Kumar, A.; Adam, T.; Reznicek, A.; Loubet, N.; He, H.; Kuss, J.; Wang, M.; Levin, T.M.; Monsieur, F.; Liu, Q.; Sreenivasan, R.; Cai, J.; Kimball, A.; Mehta, S.; Luning, S.; Zhu, Y.; Zhu, Z.; Yamamoto, T.; Bryant, A.; Lin, C.; Naczas, S.; Jagannathan, H.; Edge, L.F.; Allegret-Maret, S.; Dube, A.; Kanakasabapathy, S.; Schmitz, S.; Inada, A.; Seo, S.; Raymond, M.; Zhang, Z.; Yagishita, A.; Demarest, J.; Li, J.; Hopstaken, M.; Berliner, N.; Upham, A.; Johnson, R.; Holmes, S.; Standaert, T.; Smalley, M.; Zamdmer, N.; Ren, Z.; Wu, T.; Bu, H.; Paruchuri, V.; Sadana, D.; Narayanan, V.; Haensch, W.; O'Neill, J.; Hook, T.; Khare, M.; Doris, B.;
Impact of Circuit Degradation on FPGA Design Security
2011 / IEEE / 978-1-4577-0803-9
By: Yuan Xie; Srinivasan, S.; Han-Wei Chen; Narayanan, V.;
Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM
2011 / IEEE / 978-1-4577-0803-9
By: Mukundrajan, R.; Swaminathan, K.; Narayanan, V.; Soundararajan, N.;
Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA
2011 / IEEE / 978-1-4577-1484-9
By: Irick, K.M.; Yongseok Jin; Sungmin Bae; Cho, Y.C.P.; Narayanan, V.;
A hardware architecture for accelerating neuromorphic vision algorithms
2011 / IEEE / 978-1-4577-1921-9
By: Narayanan, V.; Yu, C.-L.; DeBole, M.; Al Maashri, A.; Chakrabarti, C.;
Energy efficient environment control system using wireless condition monitoring
2011 / IEEE / 978-1-4577-1591-4
By: Ray, A.; Sundaravaradan, J.; Kande, M.; Narayanan, V.;
A framework for accelerating neuromorphic-vision algorithms on FPGAs
2011 / IEEE / 978-1-4577-1400-9
By: Cotter, M.; Maashri, A.A.; DeBole, M.; Narayanan, V.; Chakrabarti, C.; Yu, C.-L.;
TiO2 supported Ru and Pt nano catalysts for selective hydrogenation of citral
2011 / IEEE / 978-1-4673-0178-7
By: Ananthan, S.A.; Narayanan, V.;
Detection of cortical activation and effective connectivity using Dynamic Causal Modelling through functional magnetic resonance imaging
2012 / IEEE / 978-1-4577-1991-2
By: Narayanan, V.; Ragini, B.;
When to forget: A system-level perspective on STT-RAMs
2012 / IEEE / 978-1-4673-0772-7
By: Pisolkar, R.; Swaminathan, K.; Narayanan, V.; Cong Xu;
An effective video search re-ranking for content based video retrieval
2011 / IEEE / 978-1-4673-0133-6
By: Narayanan, V.; Geetha, P.;
Synthesis, characterization and antimicrobial activity of PVA/hydroxyapatite nanocomposites
2011 / IEEE / 978-1-4673-0074-2
By: Vijayalakshmi, L.; Narayanan, V.; Dhanalakshmi, C.P.;
FPGA-accelerator system for computing biologically inspired feature extraction models
2011 / IEEE / 978-1-4673-0323-1
By: Narayanan, V.; Chakrabarti, C.; Cotter, M.; Maashri, A.A.; Chi-Li Yu; Yang Xiao; DeBole, M.;
Synthesis, characterization and electrochemical sensing properties of Fe doped V2O5 nanoparticles
2011 / IEEE / 978-1-4673-0074-2
By: Suresh, R.; Stephen, A.; Vijayalakshmi, L.; Narayanan, V.; Giribabu, K.;
Liquid phase selective hydrogenation of citral over Ru/Tio2 and Pt/Tio2 nano catalysts
2011 / IEEE / 978-1-4673-0074-2
By: Narayanan, V.; Ananthan, S.A.;
Preparation and characterization of Hg doped ZnO nanorods
2011 / IEEE / 978-1-4673-0074-2
By: Saravanan, R.; Narayanan, V.; Prakash, T.; Stephen, A.; Kumaresan, M.;
An FPGA-based accelerator for cortical object classification
2012 / IEEE / 978-1-4577-2145-8
By: Narayanan, V.; Sabarad, J.; Kestur, S.; Mi Sun Park; Irwin, M.J.;
Hazard driven test generation for SMT processors
2012 / IEEE / 978-1-4577-2145-8
By: Narayanan, V.; Singh, P.; Landis, D.L.;
A reconfigurable accelerator for neuromorphic object recognition
2012 / IEEE / 978-1-4673-0772-7
By: Kestur, S.; Sabarad, J.; Khosla, D.; Yang Chen; Narayanan, V.; Dantara, D.; Mi Sun Park;
A reconfigurable platform for the design and verification of domain-specific accelerators
2012 / IEEE / 978-1-4673-0772-7
By: Irick, K.M.; Cho, Y.C.P.; Sungho Park; Narayanan, V.;
Cadmium oxide as electrochemical probe for nitrophenols
2011 / IEEE / 978-1-4673-0074-2
By: Narayanan, V.; Suresh, R.; Giribabu, K.; Stephen, A.; Vijayalakshmi, L.;
Lateral motion of bubbles from surfaces with mini ratchet topography modifications during pool boiling- experiments and preliminary model
2012 / IEEE / 978-1-4244-9532-0
By: Thiagarajan, N.; Kapsenberg, F.; Bhavnani, S.; Narayanan, V.;
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
2012 / IEEE / 978-1-4673-0847-2
By: Kwon, U.; Wong, K.; Chudzik, M.P.; Chen, X.; Divakaruni, R.; Narayanan, V.; Krishnan, M.; Paruchuri, V.; Muncy, J.; Zhang, Y.; Salvador, D.S.; Cutler, J.; Lai, W.L.; Ramachandran, R.; Kim, I.; Bao, R.; Liu, Y.; Krishnan, S.A.; Econimikos, L.; Zhang, X.; Ortolland, C.; Thanh, L.D.; Laloe, J.; Huang, J.Y.; Edge, L.F.; Wang, H.M.; Gribelyuk, M.A.; Rath, D.L.; Bingert, R.;
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
2012 / IEEE / 978-1-4503-1199-1
By: Jog, A.; Das, C.R.; Iyer, R.; Narayanan, V.; Yuan Xie; Cong Xu; Mishra, A.K.;
High performance bulk planar 20nm CMOS technology for low power mobile applications
2012 / IEEE / 978-1-4673-0847-2
By: Huiling Shang; Jain, S.; Josse, E.; Alptekin, E.; Nam, M.H.; Kim, S.W.; Cho, K.H.; Kim, I.; Liu, Y.; Yang, X.; Wu, X.; Ciavatti, J.; Kim, N.S.; Vega, R.; Kang, L.; Meer, H.V.; Samavedam, S.; Celik, M.; Soss, S.; Utomo, H.; Ramachandran, R.; Lai, W.; Sardesai, V.; Tran, C.; Kim, J.Y.; Park, Y.H.; Tan, W.L.; Shimizu, T.; Joy, R.; Strane, J.; Tabakman, K.; Lalanne, F.; Montanini, P.; Babich, K.; Kim, J.B.; Economikos, L.; Cote, W.; Reddy, C.; Belyansky, M.; Arndt, R.; Kwon, U.; Wong, K.; Koli, D.; Levedakis, D.; Lee, J.W.; Muncy, J.; Krishnan, S.; Schepis, D.; Chen, X.; Kim, B.D.; Tian, C.; Linder, B.P.; Cartier, E.; Narayanan, V.; Northrop, G.; Menut, O.; Meiring, J.; Thomas, A.; Aminpur, M.; Park, S.H.; Lee, K.Y.; Kim, B.Y.; Rhee, S.H.; Hamieh, B.; Srivastava, R.; Koshy, R.; Goldberg, C.; Pallachalil, M.; Chae, M.; Ogino, A.; Watanabe, T.; Oh, M.; Mallela, H.; Codi, D.; Malinge, P.; Weybright, M.; Mann, R.; Mittal, A.; Eller, M.; Lian, S.; Li, Y.; Divakaruni, R.; Bukofsky, S.; Kim, J.D.; Sudijono, J.; Neumueller, W.; Matsuoka, F.; Sampson, R.;
Accelerating neuromorphic vision algorithms for recognition
2012 / IEEE / 978-1-4503-1199-1
By: DeBole, M.; Maashri, A.A.; Chakrabarti, C.; Narayanan, V.; Yang Xiao; Chandramoorthy, N.; Cotter, M.;
Emulating Mammalian Vision on Reconfigurable Hardware
2012 / IEEE / 978-1-4673-1605-7
By: Kestur, S.; Khosla, D.; Yang Chen; Narayanan, V.; Dantara, D.; Sabarad, J.; Mi Sun Park;
Enhanced x-ray emission from bacteria
2012 / IEEE
By: Krishnamurthy, M.; Mondal, Sudipta; Ray, Krishanu; Kundu, M.; Ravindra Kumar, G.; Singh, Prashant Kumar; Lad, Amit D.; Bane, Kartik; Ahmed, Saima; Narayanan, V.; Rajeev, R.; Chatterjee, Gourab;
A Reconfigurable Low-Power BDD Logic Architecture Using Ferroelectric Single-Electron Transistors
2015 / IEEE
By: Narayanan, V.; Li, X.; Liu, L.; Datta, S.;
An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
2015 / IEEE
By: Wong, K.; Kwon, U.; Bao, R.; Miao, X.; Krishnan, S.; Rausch, W.; Narayanan, V.; Grunow, S.; Wachnik, R.; Weng, W.; Li, X.;
A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter
2014 / IEEE
By: Liu, H.; Kim, M.S.; Narayanan, V.; Datta, S.; Li, X.;
Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond
2014 / IEEE
By: Ando, T.; Kannan, B.; Narayanan, V.; Krishnan, S. A.; Bruley, J.; Copel, M.; Haight, R.; Cartier, E. A.; Linder, B. P.; Kwon, U.; Lai, W. L.;
The Quantum Metal Ferroelectric Field-Effect Transistor
2014 / IEEE
By: Theis, T.N.; Narayanan, V.; Frank, M.M.; Dubourdieu, C.; Solomon, P.M.; Frank, D.J.;
Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability
2014 / IEEE
By: Kulkarni, J. P.; Saripalli, V.; Pandey, R.; Datta, S.; Narayanan, V.;
A simple model to predict fuel saving benefits with brake energy recovery methods of conventional vehicle regenerative braking system
2014 / IEEE
By: Srinivas, S.; Mariappan, V.; Narayanan, V.;
Regenerative braking scheme for conventional vehicle using ultracapacitor
2014 / IEEE
By: Srinivas, S.; Mariappan, V.; Narayanan, V.;
Investigation of critical charge and sensitive volume of the Neutron Intercepting Silicon Chip (NISC)
2013 / IEEE
By: Unlu, K.; Hossain, T. Z.; Narayanan, V.; Celik, C.;
Weighted random pattern testing based on test counts
1988 / IEEE
By: Pitchumani, V.; Narayanan, V.;
Finite difference frequency-domain treatment of open transmission structures
1990 / IEEE
By: Manela, M.; Sarkar, T.K.; Djordjevic, A.R.; Narayanan, V.;
Parallel automated test pattern generation on the Connection Machine
1989 / IEEE
By: Narayanan, V.; Pitchumani, V.; Mayor, P.;
A parallel algorithm for fault simulation on the Connection Machine
1988 / IEEE / 0-8186-0870-6
By: Narayanan, V.; Pitchumani, V.;
VIS speeds new media processing
1996 / IEEE
By: Narayanan, V.; O'Connor, J.M.; Tremblay, M.; Liang He;
Design analysis of permanent magnet DC motors with differing armature, magnet and yoke lengths
1996 / IEEE / 0-7803-2795-0
By: Anandukumaran, K.R.; Narayanan, V.; Narayanan, S.S.;
Static timing analysis for self resetting circuits
1996 / IEEE / 0-8186-7597-7
By: Chappell, B.A.; Narayanan, V.; Fleischer, B.M.;
Noise in deep submicron digital design
1996 / IEEE / 0-8186-7597-7
By: Narayanan, V.; Shepard, K.L.;
Intelligent Process Routing
1992 / IEEE / 0-8186-2615-1
By: Narayanan, V.;
Global Harmony: coupled noise analysis for full-chip RC interconnect networks
1997 / IEEE / 0-8186-8200-0
By: Zheng, G.; Elmendorf, P.C.; Narayanan, V.; Shepard, K.L.;
Conquering noise in deep-submicron digital ICs
1998 / IEEE
By: Shepard, K.L.; Narayanan, V.;
Design analysis of permanent magnet DC motors with differing armature, magnet and yoke lengths
1998 / IEEE
By: Yegna Narayanan, S.S.; Narayanan, V.; Anandakumaran Nair, K.R.;
Harmony: static noise analysis of deep submicron digital integrated circuits
1999 / IEEE
By: Narayanan, V.; Shepard, K.L.; Rose, R.;
Energy issues in multimedia systems
1999 / IEEE / 0-7803-5650-0
By: Narayanan, V.; Irwin, M.J.;
Modeling energy of the clock generation and distribution circuitry
2000 / IEEE / 0-7803-6598-4
By: Narayanan, V.; Irwin, M.J.; Duarte, D.;
Design of databus charge recovery mechanism
2000 / IEEE / 0-7803-6598-4
By: Lyuboslavsky, V.; Irwin, M.J.; Narayanan, V.; Bishop, B.;
Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks
2001 / IEEE / 0-7695-0831-6
By: Irwin, M.J.; Narayanan, V.; Duarte, D.; Kandemir, M.;
Reduction of metal-semiconductor contact resistance by embedded nanocrystals
2000 / IEEE / 0-7803-6438-4
By: Shen, Y.-M.N.; Liu, Z.; Narayanan, V.; Kan, E.C.; Kim, M.;
Low programming voltages and long retention time in metal nanocrystal EEPROM devices
2001 / IEEE / 0-7803-7014-7
By: Kan, E.C.; Gen Pei; Myongseob Kim; Narayanan, V.; Zengtao Liu;
Evaluating the impact of architectural-level optimizations on clock power
2001 / IEEE / 0-7803-6741-3
By: Narayanan, V.; Duarte, D.; Kandemir, M.; Irwin, M.J.;
Impact of technology scaling in the clock system power
2002 / IEEE / 0-7695-1486-3
By: Irwin, M.J.; Narayanan, V.; Duarte, D.;
Metal nanocrystal memories. I. Device design and fabrication
2002 / IEEE
By: Pei, G.; Narayanan, V.; Lee, C.; Liu, Z.; Kan, E.C.;
Metal nanocrystal memories-part II: electrical characteristics
2002 / IEEE
By: Kan, E.C.; Pei, G.; Narayanan, V.; Lee, C.; Liu, Z.;
An analytical power estimation model for crossbar interconnects
2002 / IEEE / 0-7803-7494-0
By: Geethanjali, E.; Irwin, M.J.; Narayanan, V.;
Embedded inductors incorporated in the design of SAW module SMT packaging
2002 / IEEE / 0-7803-7582-3
By: Mink, J.; Potter, B.R.; Narayanan, V.;
A novel quad source/drain metal nanocrystal memory device for multibit-per-cell storage
2003 / IEEE
By: Kan, E.C.; Pei, G.; Narayanan, V.; Chungho Lee; Zengtao Liu;
Leakage current: Moore's law meets static power
2003 / IEEE
By: Narayanan, V.; Kandemir, M.; Irwin, M.J.; Hu, J.S.; Kim, N.S.; Mudge, T.; Baauw, D.; Austin, T.; Flautner, K.;
Guest Editorial
2004 / IEEE
By: Piguet, C.; Narayanan, V.;
Guest Editorial
2004 / IEEE
By: Piguet, C.; Narayanan, V.;
A parallel architecture for secure FPGA symmetric encryption
2004 / IEEE / 0-7695-2132-0
By: Narayanan, V.; Brooks, R.R.; Swankoski, E.J.; Irwin, M.J.; Kandemir, M.;
Degradation of ultra-thin oxides with tungsten gates under high voltage: wear-out and breakdown transient
2004 / IEEE / 0-7803-8315-X
By: McFeely, F.R.; Narayanan, V.; Stathis, J.H.; Lombardo, S.; Palumbo, F.; Yurkas, J.J.;
Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates
2004 / IEEE / 0-7803-8289-7
By: Jamison, P.; Cabral, C., Jr.; Gusev, E.P.; Narayanan, V.; Cartier, E.; Jammy, R.; Guha, S.; Lacey, D.; Newbury, J.; D'Emic, C.; Carruthers, R.; Linder, B.; Chudzik, M.P.; Gribelyuk, M.; Callegari, A.; Zafar, S.; Cohen, S.A.; Copel, M.; Bojarczuk, N.; Frank, M.; Chan, K.K.; Steen, M.;
Dual workfunction fully silicided metal gates
2004 / IEEE / 0-7803-8289-7
By: Cabral, C., Jr.; Jammy, R.; Carruthers, R.; Kozlowski, P.; Linder, B.; Kedzierski, J.; Fang, S.; Narayanan, V.; Zafar, S.; Steegen, A.;
Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow
2004 / IEEE / 0-7803-8289-7
By: Park, D.-G.; Luo, Z.J.; Wann, C.H.; Sekiguchi, A.; Ng, H.; Rengarajan, R.; Jammy, R.; Wise, R.; Steegen, A.; Narayanan, V.; D'Emic, C.; Kozlowski, P.; Duch, E.; Kim, H.; Ku, V.; Mitchell, R.; Chakravarti, A.; Ronsheim, P.; Gluschenkov, O.; Bruley, J.; Chudzik, M.; Chou, A.; Lee, B.H.; Jamison, P.; Edleman, N.; Zhu, W.; Nguyen, P.; Wong, K.; Cabral, C.;
Dual work function metal gate CMOS using CVD metal electrodes
2004 / IEEE / 0-7803-8289-7
By: Nakamura, K.; Li, Y.; McFeely, F.R.; Callegari, A.; Narayanan, V.; Shahidi, G.; Ieong, M.; Jammy, R.; Wann, C.; Ng, H.; Duch, F.; Sikorski, E.; Jamison, P.; Lacey, D.; Kawano, Y.; Wajda, C.; Gribelyuk, M.; Cabral, C., Jr.; Milkove, K.; Nguyen, P.; Ku, V.; Steegen, A.; Cartier, E.; Zafar, S.;
A built-in self-testing method for embedded multiport memory arrays
2004 / IEEE / 0-7803-8248-X
By: Narayanan, V.; Das, S.R.; Jone, W.B.; Ghosh, S.;
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs
2004 / IEEE / 0-7803-8651-5
By: Sashikanth, M.; Chandrasekhar, V.; Sundar, E.S.; Narayanan, V.; Kamakoti, V.;
A critical examination of the basis of macroscopic quantum transport approaches
2004 / IEEE / 0-7803-8649-3
By: Narayanan, V.; Kan, E.C.;
Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage
2004 / IEEE / 0-7803-8684-1
By: Gusev, E.P.; Cabral, C., Jr.; Under, B.P.; Kim, Y.H.; Maitra, K.; Carrier, E.; Nayfeh, H.; Amos, R.; Biery, G.; Bojarczuk, N.; Callegari, A.; Carruthers, R.; Cohen, S.A.; Copel, M.; Fang, S.; Frank, M.; Guha, S.; Gribelyuk, M.; Jamison, P.; Jammy, R.; Ieong, M.; Kedzierski, J.; Kozlowski, P.; Ku, K.; Lacey, D.; LaTulipe, D.; Narayanan, V.; Ng, H.; Nguyen, P.; Newbury, J.; Paruchuri, V.; Rengarajan, R.; Shahidi, G.; Steegen, A.; Steen, M.; Zafar, S.; Zhang, Y.;
Charge trapping in aggressively scaled metal gate/high-k stacks
2004 / IEEE / 0-7803-8684-1
By: Maitra, K.; McFeely, F.R.; Kozlowski, P.; Jamison, P.; Duch, E.; D'Emic, C.; Chudzik, M.; LaTulipe, D.; Carruthers, R.; Callegari, A.; Bojarczuk, N.; Carrier, E.; Cabral, C., Jr.; Zafar, S.; Narayanan, V.; Gusev, E.P.; Steen, M.; Paruchuri, V.; Newbury, J.;
Interface engineering for enhanced electron mobilities in W/HfO/sub 2/ gate stacks
2004 / IEEE / 0-7803-8684-1
By: Andreoni, W.; Curioni, A.; Gribelyuk, M.; Jammy, R.; Feely, F.M.; Lacey, D.; Shepard, J.; D'Emic, C.; Narayanan, V.; Gusev, E.; Zafar, S.; Carrier, E.; Jamison, P.; Callegari, A.; Pignedoli, C.;
HfO/sub 2//metal stacks: determination of energy level diagram, work functions & their dependence on metal deposition
2005 / IEEE / 4-900784-00-1
By: Zafar, S.; Jammy, R.; Cabral, C., Jr.; Gusev, E.; Narayanan, V.; Jamison, P.; McFeely, F.R.; Callegari, A.;
High performance FDSOI CMOS technology with metal gate and high-k
2005 / IEEE / 4-900784-00-1
By: Rubino, J.; Chang, L.; Narayanan, V.; Boyd, D.; Steen, M.; Linder, B.P.; Kim, Y.H.; Doris, B.; Leong, M.; Guarini, K.W.; Jammy, R.; Kozlowski, P.; D'Emic, C.; Carruthers, R.; Walker, J.F.; Newbury, J.; Kirsch, P.; Zhang, Y.; Babich, K.; Wong, L.; Shi, L.; Sikorski, E.; Topol, A.; Sleight, J.;
Role of oxygen vacancies in V/sub FB//V/sub t/ stability of pFET metals on HfO/sub 2/
2005 / IEEE / 4-900784-00-1
By: Paruchuri, V.K.; Basker, V.S.; Linder, B.P.; Copel, M.; Jamison, P.; Narayanan, V.; McFeely, F.R.; Cartier, E.; Shahidi, G.; Jammy, R.; Guha, S.; Deligianni, H.; Rubino, J.; Sleight, J.; Steen, M.; Shaw, T.; Carruthers, R.; Lim, D.; Haight, R.;
Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility
2005 / IEEE / 0-7803-9058-X
By: Ieong, M.; Jammy, R.; Guha, S.; Oldiges, P.; Medeiros, D.R.; Newbury, J.S.; Kozlowski, P.M.; Wang, X.; Maitra, K.; Cohen, S.A.; Copel, M.; Steen, M.L.; Lee, K.L.; Jamison, P.C.; Gusev, E.P.; Cartier, E.A.; Zafar, S.; Linder, B.; Bojarczuk, N.; Narayanan, V.; Paruchuri, V.K.; Frank, M.M.; Shahidi, G.;
Ultra-thin SOI replacement gate CMOS with ALD TaN/high-k gate stack
2005 / IEEE / 0-7803-9058-X
By: Li, Y.; Hagan, J.; Boyd, D.; Jamison, P.; Settlemyer, K.; Park, D.G.; Doris, B.; Leong, M.; Jammy, R.; Guarini, K.; Gousev, E.; Callegari, S.; Narayanan, V.; Linder, B.; Dobuzinsky, D.; Mezzapelli, J.; Staendert, T.;
A built-in self-testing method for embedded multiport memory arrays
2005 / IEEE
By: Ghosh, S.; Narayanan, V.; Das, S.R.; Jone, W.-B.;
Tungsten-rhenium filament lifetime variability in low pressure oxygen environments
2005 / IEEE
By: Roddy, P.A.; Narayanan, V.; Rajagopal, N.; Medikonduri, R.; Earle, G.D.;
Asymmetric electric field enhancement in nanocrystal memories
2005 / IEEE
By: Narayanan, V.; Ganguly, U.; Chungho Lee; Kan, E.C.; Jinsook Kim; Tuo-Hung Hou;
Soft errors issues in low-power caches
2005 / IEEE
By: Irwin, M.J.; Kandemir, M.; Narayanan, V.; Lin Li; Degalahal, V.;
Reliability concerns in embedded system designs
2006 / IEEE
By: Xie, Y.; Narayanan, V.;
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks
2006 / IEEE / 0-7695-2502-4
By: Park, D.; Nicopoulos, C.; Richardson, T.D.; Degalahal, V.; Das, C.; Yuan Xie; Narayanan, V.;

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