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Author: Nara, Y.

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Ultrathin Barrier Formation Using Combination of Manganese Oxide Encapsulation and Self-Aligned Copper Silicon Nitride Barriers for Copper Wiring in Future LSI Interconnects
2011 / IEEE
By: Kudo, H.; Nara, Y.; Kitada, H.; Owada, T.; Sakai, H.; Haneda, M.; Ochimizu, H.; Sunayama, M.; Tabira, T.; Ohtsuka, N.;
A 0.5- mu m EEPROM cell using poly-Si TFT technology
1993 / IEEE
By: Momiyama, Y.; Sato, A.; Ito, T.; Arimoto, Y.; Sugii, T.; Nara, Y.;
21 psec switching 0.1 /spl mu/m-CMOS at room temperature using high performance Co salicide process
1993 / IEEE / 0-7803-1450-6
By: Nara, Y.; Fukano, T.; Goto, K.; Yamazaki, T.; Ito, T.; Sugii, T.;
Giga-bit DRAM cells with low capacitance and low resistance bit-lines on buried MOSFETs and capacitors by using bonded SOI technology-reversed stacked capacitor (RSTC) cell
1995 / IEEE / 0-7803-2700-4
By: Fukano, T.; Nara, Y.; Asano, K.; Horie, H.; Nakamura, S.; Sasaki, N.;
A digital color camera LSI chip set for multiple applications
1997 / IEEE
By: Miyazaki, H.; Osawa, N.; Kumagai, D.; Nakajima, T.; Taura, Y.; Gamou, N.; Sato, M.; Hanagata, T.; Mori, H.; Nara, Y.; Nakada, H.; Yamamoto, S.;
Stitching-Error-Free Overlay Metrology For EB Lithography Using "One-Shot" Inspection Target Mark
1998 / IEEE / 4-930813-83-2
By: Sato, M.; Nagata, T.; Takahashi, K.; Asano, K.; Nara, Y.;
Embedded DRAM technology compatible to the 0.13 /spl mu/m high-speed logics by using Ru pillars in cell capacitors and peripheral vias
1998 / IEEE / 0-7803-4774-9
By: Nakabayashi, M.; Kojima, M.; Fukuda, M.; Suzuki, R.; Hatada, A.; Kurahashi, T.; Kimura, T.; Kobayashi, M.; Tsunoda, H.; Minakata, H.; Satoh, A.; Kosemura, K.; Shido, H.; Kosugi, M.; Nakamura, S.; Sasaki, N.; Fukano, T.; Nara, Y.;
Extraction of the trap density at the gate periphery using the gated diode array for giga-bit DRAMs
1999 / IEEE / 0-7803-5270-X
By: Nara, Y.; Kojima, M.; Suzuki, H.;
Coulomb interaction effect correction in e-beam block exposure lithography
1999 / IEEE / 4-930813-97-2
By: Hoshino, H.; Manabe, Y.; Nara, Y.; Takahashi, K.; Machida, Y.;
Tools for shifting human context into disasters: a case-based guideline for computer-aided earthquake proofs
2000 / IEEE / 0-7803-6400-7
By: Nara, Y.; Ohsawa, Y.;
Decision trees as a model of chance perception
2001 / IEEE / 0-7803-7078-3
By: Nara, Y.; Ohsawa, Y.;
Impact of highly-doped s/d extension on the current drivability and reliability in 0.15/spl mu/m CMOS
1994 / IEEE
By: Nara, Y.; Sugii, T.; Yamazaki, T.; Kurata, H.;
A 0.5-/spl mu/m EEPROM cell using poly-si TFT technology
1993 / IEEE
By: Arimoto, Y.; Sugii, T.; Nara, Y.; Momiyama, Y.; Sato, A.; Ito, T.;
Understanding Internet users on double helical model of chance-discovery process
2002 / IEEE / 0-7803-7620-X
By: Ohsawa, Y.; Nara, Y.;
Interactive extraction of phonemic variation rules in continuous speech
1986 / IEEE
By: Kimura, S.; Nara, Y.;
Extraction of phonemic variation rules in continuous speech spoken by multiple speakers
1987 / IEEE
By: Kimura, S.; Nara, Y.;
Large-vocabulary spoken word recognition using simplified time-warping patterns
1982 / IEEE
By: Iwata, K.; Nara, Y.; Tanahashi, J.; Sasaki, S.; Kimura, S.; Kobayashi, A.; Kijima, Y.;
Speaker adaptation in large-vocabulary voice recognition
1984 / IEEE
By: Kobayashi, A.; Nara, Y.; Kijima, Y.; Kimura, S.;
New nonvolatile memory with charge-trapping sidewall
2003 / IEEE
By: Fukuda, M.; Nara, Y.; Nakanishi, T.;
Face recognition using improved principal component analysis
2003 / IEEE / 0-7803-8165-3
By: Jianming Yang; Nara, Y.; Suematsu, Y.;
Low energy implantation technology with molecular ion beam
2004 / IEEE / 0-7803-8511-X
By: Naito, M.; Sakai, S.; Nagayama, T.; Umisedo, S.; Nagai, N.; Tanjyo, M.; Nara, Y.; Hamamoto, N.; Aoyama, T.;
Face detection using the shape of face with both color and edge
2004 / IEEE / 0-7803-8643-4
By: Yang, Y.; Nara, Y.; Suematsu, Y.;
Improvement in NBTI by catalytic-CVD silicon nitride for hp-65nm technology
2005 / IEEE / 4-900784-00-1
By: Nara, Y.; Amai, H.; Saitou, T.; Torii, K.; Watanabe, T.; Inumiya, S.; Kitazoe, M.; Robata, T.; Matsuki, T.; Yamamura, M.; Akasaka, Y.; Yuba, Y.;
Direct measurement of effects of shallow-trench isolation on carrier profiles in sub-50 nm N-MOSFETs
2005 / IEEE / 4-900784-00-1
By: Aoyama, T.; Kubo, T.; Tagawa, Y.; Momiyama, Y.; Fukutome, H.; Nara, Y.; Arimoto, H.;
Impact of electrode-side chemical structures on electron mobility in metal/HfO/sub 2/ MISFETs with sub-1nm EOT
2005 / IEEE / 4-900784-00-1
By: Nara, Y.; Ootsuka, F.; Ogawa, O.; Kamiyama, S.; Akasaka, Y.; Sasaki, T.; Miyagawa, K.; Shiraishi, K.;
Amorphous-silicon image sensor IC
1980 / IEEE
By: Nara, Y.; Hayama, H.; Matsumura, M.; Ishibashi, K.;
A novel amorphous-silicon inverter circuit
1980 / IEEE
By: Uchida, Y.; Nara, Y.; Matsumura, M.;
An amorphous silicon integrated inverter
1982 / IEEE
By: Matsumara, M.; Nara, Y.;
IIIB-7 high speed operation of amorphous-silicon charge-coupled devices
1983 / IEEE
By: Matsumura, M.; Kishida, S.; Uchida, Y.; Nara, Y.;
Proposed vertical-type amorphous-silicon field-effect transistors
1984 / IEEE
By: Nara, Y.; Uchida, Y.; Matsumura, M.;
The role of nitrogen incorporation in Hf-based high-k dielectrics: reduction in electron charge traps
2005 / IEEE / 0-7803-9203-5
By: Nara, Y.; Yamada, K.; Ohno, T.; Yamabe, K.; Watanabe, H.; Umezawa, N.; Boero, M.; Torii, K.; Shiraishi, K.; Chikyow, T.;
Decaborane ion implantation for sub-40-nm gate-length PMOSFETs to enable formation of steep ultra-shallow junction and small threshold voltage fluctuation
2005 / IEEE / 4-9902158-6-9
By: Fukuda, M.; Aoyama, T.; Nagayama, T.; Tanjo, M.; Hamamoto, N.; Umisedo, S.; Nara, Y.;
A thermally-stable sub-0.9nm EOT TaSix/HfSiON gate stack with high electron mobility, suitable for gate-first fabrciation of hp45 LOP devices
2005 / IEEE / 0-7803-9268-X
By: Torii, K.; Ootsuka, F.; Matsuki, T.; Akasaka, Y.; Inumiya, S.; Nara, Y.;
Universal theory of workfunctions at metal/Hf-based high-k dielectrics interfaces - guiding principles for gate metal selection
2005 / IEEE / 0-7803-9268-X
By: Akasaka, Y.; Miyazaki, S.; Shiraishi, K.; Yamada, K.; Nara, Y.; Green, M.L.; Chikyow, T.; Watanabe, H.; Ohmori, K.; Ahmet, P.; Ohta, A.; Furutou, H.; Torii, K.; Nakamura, G.; Nakaoka, T.; Nakayama, T.;
A Novel Remote Reactive Sink Layer Technique for the Control of N and O Concentrations in Metal/High-k Gate Stacks
2006 / IEEE / 1-4244-0005-8
By: Nakamura, N.; Umezawa, N.; Shiraishi, K.; Akasaka, Y.; Ogawa, O.; Nara, Y.; Ootsuka, F.; Chikyow, T.; Kasuya, T.;
Determination of Time to Breakdown of 0.8-1.2 nm EOT HfSiON Gate Dielectrics with Poly-Si and Metal Gate Electrodes
2006 / IEEE / 0-7803-9498-4
By: Torii, K.; Inumiya, S.; Nara, Y.;
Theory of Fermi Level Pinning of High-k Dielectrics
2006 / IEEE / 1-4244-0404-5
By: Takeuchi, H.; Akasaka, Y.; Watanabe, H.; Umezawa, N.; Shiraishi, K.; Nara, Y.; Yamada, K.; Tsu-Jae King Liu; Chikyow, T.;
Novel Silicide-Cladded Uniaxially-Strained Thin-Body SOI CMOS FETs Featuring Floating Body Modulation Induced by Hf-based Gate Dielectric
2006 / IEEE / 1-4244-0289-1
By: Satake, H.; Watanabe, T.; Ootsuka, F.; Toriumi, A.; Nara, Y.; Watanabe, M.; Migita, S.; Mise, N.;
High-k/metal gate stack technology for advanced CMOS
2006 / IEEE / 1-4244-0161-5
By: Nara, Y.; Ohji, Y.; Inumiya, S.; Ootsuka, F.;
Controllability of flatband voltage in high-k gate stack structures - remarkable advantages of La/sub 2/O/sub 3/ over HfO/sub 2/
2006 / IEEE / 1-4244-0161-5
By: Nakayama, T.; Chang, K.-S.; Nakajima, K.; Umezawa, N.; Yoshitake, M.; Akasaka, Y.; Watanabe, H.; Yamabe, K.; Shiraishi, K.; Ahmet, P.; Ohmori, K.; Chikyow, T.; Yamada, K.; Iwai, H.; Green, M.L.; Nara, Y.; Kakushima, K.;
Physics of interfaces between gate electrodes and high-k dielectrics
2006 / IEEE / 1-4244-0161-5
By: Takeuchi, H.; Akasaka, Y.; Shiraishi, K.; Yamada, K.; Iwai, H.; King Liu, T.-J.; Nara, Y.; Chikyow, T.; Toii, K.; Ahmet, P.; Ohmori, K.; Umezawa, N.; Watanabe, H.; Ohta, A.; Nakaoka, T.; Miyazaki, S.; Nakayama, T.;
Oxidation process of HfO/sub 2//SiO/sub 2//Si structures observed by high-resolution RBS
2006 / IEEE / 1-4244-0161-5
By: Watanabe, H.; Nara, Y.; Kamiyama, S.; Torii, K.; Kimura, K.; Uematsu, M.; Shiraishi, K.; Suzuki, M.; Nakajima, K.; Zhao Ming; Yamada, K.; Chikyow, T.;
Role of Nitrogen Atoms in Reduction of Electron Charge Traps in Hf-Based High- $\kappa$ Dielectrics
2007 / IEEE
By: Umezawa, N.; Shiraishi, K.; Torii, K.; Boero, M.; Nara, Y.; Watanabe, H.; Yamabe, K.; Ohno, T.; Yamada, K.; Chikyow, T.;
Investigation of Irregular Strand Positions Causing Additional AC Losses in CIC Conductor
2007 / IEEE
By: Nunoya, Y.; Hamajima, T.; Nara, Y.; Tsuda, M.; Okuno, K.; Sato, H.; Yagai, T.; Takahata, K.;
Study of Ultra-shallow Junctions Formed by Flash Lamp Annealing to Reveal Dopant Activation Phenomenon
2007 / IEEE / 1-4244-1103-3
By: Onizawa, T.; Aoyama, T.; Kato, S.; Ohji, Y.; Nara, Y.;
High Through-Put Parallel Biomolecules Sorting Microsystem with Three Dimensional PDMS Stack
2007 / IEEE / 1-4244-0841-5
By: Sugino, H.; Nara, Y.; Shoji, S.; Funatsu, T.; Shirasaki, Y.; Arakawa, T.;
Reliability Perspective of High-k Gate Stack Assessed by Temperature Dependence of Dielectric Breakdown
2007 / IEEE / 978-4-900784-03-1
By: Ota, H.; Nara, Y.; Ootsuka, F.; Inumiya, S.; Akasaka, Y.; Nabatame, T.; Satake, H.; Horikawa, T.; Okada, K.; Toriumi, A.;
Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS
2007 / IEEE / 978-4-900784-03-1
By: Miyazaki, S.; Nakajima, K.; Ohta, A.; Watanabe, H.; Shiraishi, K.; Sugita, Y.; Kadoshima, M.; Ohji, Y.; Nara, Y.; Aoyama, T.; Matsuki, T.; Kurosawa, E.; Aminaka, T.; Yamada, K.; Chikyow, T.;
R-2: The status and prognosis for high-�/ metal gate transistors
2007 / IEEE / 978-4-900784-03-1
By: Khare, M.; Nara, Y.; Tsunashima, Y.; Lee, B.-H.; Lee, J.C.; Imai, K.; Chung, U-I.; Bohr, M.;
Wide Controllability of Flatband Voltage by Tuning Crystalline Microstructures in Metal Gate Electrodes
2007 / IEEE / 978-1-4244-1507-6
By: Ohmori, K.; Yamada, K.; Yamabe, K.; Shiraishi, K.; Ohji, Y.; Nara, Y.; Sugita, Y.; Ishikawa, A.; Adachi, T.; Nakajima, K.; Watanabe, H.; Hosoi, T.; Chikyow, T.;
Single Metal/Dual High-k Gate Stack with Low Vth and Precise Gate Profile Control for Highly Manufacturable Aggressively Scaled CMISFETs
2007 / IEEE / 978-1-4244-1507-6
By: Mise, N.; Ohji, Y.; Nara, Y.; Ono, T.; Sato, M.; Murayama, K.; Kamiyama, S.; Eimori, T.; Morooka, T.;
Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate
2007 / IEEE / 978-1-4244-1507-6
By: Yoshinaga, H.; Miyazaki, S.; Kurosawa, E.; Ohta, A.; Aminaka, T.; Sato, M.; Matsuki, T.; Kadoshima, M.; Ohji, Y.; Nara, Y.; Aoyama, T.; Yamada, K.; Yamabe, K.; Shiraishi, K.;
Band Edge Gate First HfSiON/Metal Gate n-MOSFETs using ALD-La2O3 Cap Layers Scalable to EOT=0.68 nm for hp 32 nm Bulk Devices with High Performance and Reliability
2007 / IEEE / 978-1-4244-1507-6
By: Nara, Y.; Aoyama, T.; Ootuka, M.; Kitajima, M.; Kurosawa, E.; Miura, T.; Kamiyama, S.;
Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- $k$ FETs
2008 / IEEE
By: Watanabe, T.; Shirai, K.; Katakami, A.; Ootsuka, F.; Tanjyo, M.; Nakata, H.; Ohji, Y.; Nara, Y.; Eimori, T.; Aoyama, T.; Kitajima, M.;
Investigation of a Mechanism Forming Irregular Loops in Large CIC Conductor
2008 / IEEE
By: Yagai, T.; Takahata, K.; Okuno, K.; Nunoya, Y.; Hamajima, T.; Tsuda, M.; Ohmura, J.; Nara, Y.;
Cluster Ion Implantation for beyond 45nm node novel device applications
2008 / IEEE / 978-1-4244-1737-7
By: Tanjyo, M.; Nagayama, T.; Horsky, T.; Jacobson, D.; Krull, W.; Saker, K.; Ohji, Y.; Nara, Y.; Eimori, T.; Aoyama, T.; Kitajima, M.; Nakata, H.; Watanabe, T.; Shirai, K.; Katakami, A.; Ootsuka, F.; Nagai, N.; Matsumoto, T.; Maehara, N.; Koga, Y.; Umisedo, S.; Hamamoto, N.;
Flash lamp annealing in diluted oxygen for low sheet resistance and ultra-shallow junctions: Suppression of wet-cleaning-induced sheet-resistance degradation
2008 / IEEE / 978-1-4244-1737-7
By: Ohji, Y.; Nara, Y.; Onizawa, T.; Aoyama, T.; Kato, S.;
Study of boron activation by flash lamp annealing from a view of depth dependence in silicon substrate
2008 / IEEE / 978-1-4244-1737-7
By: Kato, S.; Aoyama, T.; Ohji, Y.; Nara, Y.; Onizawa, T.; Yamaguchi, K.;
Cathode electron injection breakdown model and work function dependent TDDB lifetime for high-k / metal gate stack pMOSFETs
2008 / IEEE / 978-1-4244-2049-0
By: Hasunuma, R.; Yamada, K.; Shiraishi, K.; Miyazaki, S.; Aoyama, T.; Yamabe, K.; Sato, M.; Ohji, Y.; Nara, Y.;
Characterization of leakage behaviors of high-k gate stacks by electron-beam-induced current
2008 / IEEE / 978-1-4244-2049-0
By: Yamabe, K.; Chikyow, T.; Takase, M.; Fukata, N.; Sekiguchi, T.; Hasumuma, R.; Yamada, K.; Chen, J.; Nara, Y.; Sato, M.;
Fabrication process controlled pre-existing and charge - discharge effect of hole traps in NBTI of high-k / metal gate pMOSFET
2008 / IEEE / 978-1-4244-2049-0
By: Tamura, C.; Sato, M.; Ohji, Y.; Nara, Y.; Aoyama, T.; Hasunuma, R.; Yamada, K.; Shiraishi, K.; Yamabe, K.;
New findings in nano-scale interface physics and their relations to nano-CMOS technologies
2006 / IEEE / 978-1-4244-0603-6
By: Shiraishi, K.; Yamada, K.; Nara, Y.; Chikyow, T.; Ahmet, P.; Ohmori, K.; Watanabe, H.; Nakaoka, T.; Miyazaki, S.; Nakayama, T.; Torii, K.; Akasaka, Y.;
Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure -
2008 / IEEE / 978-1-4244-1802-2
By: Kadoshima, M.; Ohji, Y.; Nara, Y.; Aoyama, T.; Yamada, K.; Chikyo, T.; Shiraishi, K.; Miyazaki, S.; Kitajima, M.; Kurosawa, E.; Aminaka, T.; Hayashi, M.; Sato, M.; Mise, N.; Matsuki, T.;
Physical understanding of the reliability improvement of dual high-k CMOSFETs with the fifth element incorporation into HfSiON gate dielectrics
2008 / IEEE / 978-1-4244-1802-2
By: Miyazaki, S.; Uedono, A.; Yamabe, K.; Chikyow, T.; Adachi, T.; Shiraishi, K.; Morooka, T.; Kadoshima, M.; Kamiyama, S.; Mise, N.; Umezawa, N.; Sato, M.; Ohji, Y.; Nara, Y.; Eimori, T.; Aoyama, T.; Yamada, K.;
Proposal of Single Metal/Dual High-$k$ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control
2009 / IEEE
By: Ono, T.; Eimori, T.; Morooka, T.; Mise, N.; Sato, M.; Mise, N.; Ohji, Y.; Nara, Y.; Kamiyama, S.;
Gate-first high-k/metal gate stack for advanced CMOS technology
2008 / IEEE / 978-1-4244-2185-5
By: Kamiyama, S.; Morooka, T.; Kadoshima, M.; Mise, N.; Nara, Y.; Matsuki, T.; Eimori, T.; Ohji, Y.; Aoyama, T.; Ono, T.; Sato, M.;
Theoretical investigations on metal/high-k interfaces
2008 / IEEE / 978-1-4244-2185-5
By: Shiraishi, K.; Yamada, K.; Nara, Y.; Watanabe, H.; Akasaka, Y.; Ohta, A.; Miyazaki, S.; Nakayama, T.;
Systematic Study of Vth controllability using ALD-Y2O3, La2O3, and MgO2 layers with HfSiON/metal gate first n-MOSFETs for hp 32 nm bulk devices
2008 / IEEE / 978-1-4244-2377-4
By: Kamiyama, S.; Ishikawa, D.; Kurosawa, E.; Nakata, H.; Ohji, Y.; Ootuka, M.; Aoyama, T.; Nara, Y.; Kitajima, M.;
Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with pre-existing and stress-induced defects
2008 / IEEE / 978-1-4244-2377-4
By: Eimori, T.; Shiraishi, K.; Kamiyama, S.; Mise, N.; Nakamura, M.; Morooka, T.; Tachibana, A.; Sugino, S.; Arimura, H.; Shimokawa, J.; Umezawa, N.; Sato, M.; Ohji, Y.; Nara, Y.; Nabatame, T.; Aoyama, T.; Yamada, K.; Watanabe, H.; Yamabe, K.;
Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates
2008 / IEEE / 978-1-4244-2377-4
By: Morooka, T.; Ishikawa, D.; Matsuki, T.; Ohmori, K.; Yamada, K.; Aminaka, T.; Nara, Y.; Shiraishi, K.; Chikyow, T.; Sugita, Y.;
Effective-Work-Function Control by Varying the TiN Thickness in Poly-Si/TiN Gate Electrodes for Scaled High- $k$ CMOSFETs
2009 / IEEE
By: Shiraishi, K.; Kadoshima, M.; Miyazaki, S.; Matsuki, T.; Chikyo, T.; Ohji, Y.; Nara, Y.; Aoyama, T.; Yamada, K.;
Advanced BEOL integration using porous low-k (k=2.25) material with charge damage-less electron beam cure technique
2009 / IEEE / 978-1-4244-4492-2
By: Fukuyama, S.; Tsukune, A.; Asami, N.; Sakoda, T.; Ochimizu, H.; Kudo, H.; Kouno, T.; Watatani, H.; Ohara, N.; Owada, T.; Kase, M.; Nara, Y.; Ohkura, Y.; Nakamura, T.; Nakaishi, M.;
Novel low-k SiOC (k=2.4) with superior tolerance to direct polish and ashing for advanced BEOL integration
2009 / IEEE / 978-1-4244-4492-2
By: Watatani, H.; Uedono, A.; Osada, T.; Takesako, S.; Kudo, H.; Kirimura, T.; Kouno, T.; Iba, Y.; Ohara, N.; Akiyama, S.; Owada, T.; Asami, N.; Kase, M.; Nara, Y.;
Scaling challenges of MOSFET for 32nm node and beyond
2009 / IEEE / 978-1-4244-2784-0
By: Nara, Y.;
Systematic study of the relationship between 1/� noise, interface state defects and mobility ddgradtion of high-K /metal CMOSFETs on (110) and (100) substrate
2009 / IEEE / 978-1-4244-2888-5
By: Nara, Y.; Aoyama, T.; Sato, M.; Ohji, Y.;
Electron beam induced current investigation of stress-induced leakage and breakdown processes in high-k stacks
2009 / IEEE / 978-1-4244-2888-5
By: Takase, M.; Fukata, N.; Sekiguchi, T.; Chen, J.; Yamada, K.; Chikyow, T.; Nara, Y.; Sato, M.; Yamabe, K.; Hasunuma, R.;
Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies
2009 / IEEE / 978-1-4244-5641-3
By: Minakata, H.; Takahashi, H.; Nara, Y.; Kase, M.; Tamura, N.; Shiqin Xiao; Morisaki, Y.; Ikeda, K.; Sakoda, T.; Nishigaya, K.; Nakabayashi, M.; Morioka, H.;
Characterization of millisecond-anneal-induced defects in SiON and SiON/Si interface by gate current fluctuation measurement
2010 / IEEE / 978-1-4244-5429-7
By: Kubo, T.; Hori, M.; Sakoda, T.; Nara, Y.; Kase, M.; Hashimoto, K.; Kaneta, C.; Matsuyama, H.; Tosaka, Y.; Nishigaya, K.; Mori, T.; Tamura, N.; Tanahashi, K.; Ono, K.; Mori, H.; Kobayashi, Y.; Minakata, H.;

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