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Author: Nagaraj, N.S.

Results

A new optimizer for performance optimization of integrated circuits by device sizing
1993 / IEEE / 0-7803-1281-3
By: Nagaraj, N.S.;
Approximate computation of signal characteristics of on-chip RC interconnect trees
1994 / IEEE / 0-7803-1915-X
By: Nagaraj, N.S.; Harward, M.; Krivacek, P.;
OPSYN - OASYS Based Pseudosynthesis Tool
1992 / IEEE / 0-8186-2465-5
By: Nagaraj, N.S.;
WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits
1992 / IEEE / 0-8186-2465-5
By: Ramesh, R.; Nagaraj, N.S.; Padmini, N.; Nagaraj, S.; Sachidanand, V.;
A practical approach to static signal electromigration analysis
1998 / IEEE / 0-89791-964-5
By: Cano, F.; Nagaraj, N.S.; Young, D.; Haznedar, H.;
Bridging the gap between TCAD and ECAD methodologies in deep sub-micron interconnect extraction and analysis
1999 / IEEE / 0-7695-0013-7
By: Nagaraj, N.S.; Cantrell, C.; Balsara, P.;
Tutorial on interconnect modeling, signal integrity and reliability verification in deep sub-micron digital designs
1999 / IEEE / 0-7803-5632-2
By: Cantrell, C.; Balsara, P.; Nagaraj, N.S.;
Performance and reliability verification of C6201/C6701 digital signal processors
1999 / IEEE / 0-7695-0406-X
By: Cano, F.; Nagaraj, N.S.; Kapoor, D.; Thiruvengadam, S.;
A practical approach to crosstalk noise verification of static CMOS designs
2000 / IEEE / 0-7695-0487-6
By: Young, D.; Cano, F.; Nagaraj, N.S.; Das, M.; Vohra, D.;
Full-chip signal interconnect analysis for electromigration reliability
2000 / IEEE / 0-7695-0525-2
By: Nagaraj, N.S.; Rochel, S.;
Crosstalk noise verification in digital designs with interconnect process variations
2001 / IEEE / 0-7695-0831-6
By: Balsara, P.; Nagaraj, N.S.; Cantrell, C.;
A 600MHz VLIW DSP
2002 / IEEE / 0-7803-7335-9
By: Agarwala, S.; Koeppen, P.; Simar, R.; Nagaraj, N.S.; Luong Nguyen; Groves, P.; Quang-Dieu An; Duc Bui; Krishnan, M.; Mahmood, H.; Apostol, J.; Common, N.; Castille, R.; Anderson, T.; Hill, A.; Ales, M.; Damodaran, R.; Nardini, L.; Wiley, P.; Mullinnix, S.; Leach, J.; Lell, A.; Gill, M.; Golston, J.; Hoyle, D.; Rajagopal, A.; Chachad, A.; Agarwala, M.;
A 600 MHz VLIW DSP
2002 / IEEE / 0-7803-7335-9
By: Ales, M.; Damodaran, R.; Hill, A.; Anderson, T.; Koeppen, P.; Agarwala, S.; Simar, R.; Nagaraj, N.S.; Nguyen, L.; Groves, P.; Quang-Dieu An; Duc Bui; Krishnan, M.; Mahmood, H.; Apostol, J.; Common, N.; Castille, R.; Agarwala, M.; Chachad, A.; Rajagopal, A.; Hoyle, D.; Golston, J.; Gill, M.; Lell, A.; Leach, J.; Mullinnix, S.; Wiley, P.; Nardini, L.;
Tutorial on modeling parasitic coupling effects in reliability verification
2002 / IEEE / 0-7695-1441-3
By: Nagaraj, N.S.; Balsara, P.; Cantrell, C.;
A 600-MHz VLIW DSP
2002 / IEEE
By: Agarwala, S.; Elappuparackal, T.T.; Hill, A.; Ales, M.D.; Damodaran, R.; Wiley, P.; Mullinnix, S.; Leach, J.; Lell, A.; Gill, M.; Rajagopal, A.; Chachad, A.; Agarwala, M.; Apostol, J.; Krishnan, M.; Duc Bui; Quang An; Nagaraj, N.S.; Wolf, T.; Anderson, T.;
Benchmarks for interconnect parasitic resistance and capacitance
2003 / IEEE / 0-7695-1881-8
By: Cantrell, C.; Singh, A.; Bonifield, T.; Nagaraj, N.S.; Cano, F.; Balsara, P.; Kulkarni, M.; Narasimha, U.;
A systematic approach to interconnect modeling and process monitoring
2003 / IEEE / 0-7803-7797-4
By: Kulkarni, M.; Nagaraj, N.S.; Zabierek, C.; Hossain, I.; Usha Narasimha; Bonifield, T.;
A 800 MHz system-on-chip for wireless infrastructure applications
2004 / IEEE / 0-7695-2072-3
By: Hill, A.; Krishnan, M.; Rajagopal, A.; Wiley, P.; Agarwala, S.; Karlovich, C.; Graber, J.; Webster, B.; Groves, P.; Gill, M.; Kroeger, T.; Nguyen, L.; Damodaran, R.; Nagaraj, N.S.; Wolf, T.; Narasimha, U.; Castille, K.; Apostol, J.; Chachad, A.; Heping Yue; Flores, J.; Mullinnix, S.; Anderson, T.; Nardini, L.;
Interconnect modeling for copper/low-k technologies
2004 / IEEE / 0-7695-2072-3
By: Singh, A.; Bonifield, T.; Nagaraj, N.S.; Balsara, P.; Griesmer, R.;
Impact of selective process bias (SPB) of interconnects on circuit delay
2004 / IEEE / 0-7803-8713-9
By: Viet Le; Marshall, A.; Nagaraj, N.S.; Kulkarni, M.;
The impact of inductance on transients affecting gate oxide reliability
2005 / IEEE / 0-7695-2264-5
By: Nagaraj, N.S.; Cantrell, C.; Balsara, P.; Hunter, W.R.;
A 65 nm CMOS technology for mobile and digital signal processing applications
2004 / IEEE / 0-7803-8684-1
By: Chatterjee, A.; Yoon, J.; Tsao, A.; Ashburn, S.; Scott, D.; Nagaraj, N.S.; Wu, J.; Houston, T.; Rosal, J.; Jain, M.; Jacobs, J.; Williams, B.; Crenshaw, D.; Yang, J.Y.; Mosher, D.; Adam, L.; Mehrotra, M.; Mair, H.; Aldrich, D.; Meek, C.; Zhang, G.; Kirmse, K.; Quevedo-Lopez, M.; Olsen, L.; Kim, T.; Hong, Q.Z.; Zhao, S.; Tang, S.; Sadra, K.; Crank, S.; Mogul, H.; Aggarwal, R.; Chatterjee, B.; Lytle, S.; Lin, C.T.; Lee, K.D.; Kim, J.;
Impact of interconnect technology scaling on SOC design methodologies
2005 / IEEE / 0-7803-8752-X
By: Chidambaram, P.R.; Hunter, W.R.; Nagaraj, N.S.; Shichijo, H.; Hill, A.; Narasimha, U.; Garibay, T.Y.;
BEOL variability and impact on RC extraction
2005 / IEEE / 1-59593-058-2
By: Nagaraj, N.S.; Hill, A.; Le, V.; Narasimha, U.; Bittlestone, C.; Singh, A.; Bonifield, T.;
SmartExtract: accurate capacitance extraction for SOC designs
2006 / IEEE / 0-7695-2502-4
By: Nagaraj, N.S.; Hill, A.; Narasimha, U.;
Optimizing Interconnect for Performance in Standard Cell Library
2006 / IEEE / 1-4244-0386-3
By: Kothamasu Siva; Dharin Shah; Nagaraj, N.S.; Girishankar, G.;
Moore's Law: Another casualty of the financial meltdown?
2009 / IEEE / 978-1-6055-8497-3
By: Radojcic, R.; Gavrielov, M.; Burns, J.; Joyner, W.; Rickert, P.; Puri, R.; Nagaraj, N.S.; Cong, J.; Stork, H.;

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