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Author: Morino, M.

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A Comparative Evaluation of Control Interfaces for a Robotic-Aided Endoscopic Capsule Platform
2012 / IEEE
By: Arezzo, A.; Salerno, M.; Valdastri, P.; Lucarini, G.; Menciassi, A.; Ciuti, G.; Dario, P.; Morino, M.;
A 29-ns 64-Mb DRAM with hierarchical array architecture
1996 / IEEE
By: Takahashi, T.; Nakamura, M.; Sato, K.; Tachibana, T.; Kajigaya, K.; Songsu Cho; Akiba, T.; Tadaki, Y.; Komatsuzaki, K.; Asano, I.; Sekiguchi, T.; Morino, M.; Kitsukawa, G.;
A 29 ns 64 Mb DRAM with hierarchical array architecture
1995 / IEEE / 0-7803-2495-1
By: Asano, I.; Sekiguchi, T.; Morino, M.; Takahashi, T.; Kitsukawa, G.; Akiba, T.; Komatsuzaki, K.; Nakamura, M.; Satoh, K.; Tachibana, T.; Kajigaya, K.; Songsu, C.; Tadaki, Y.;
1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMs
1998 / IEEE / 0-7803-4774-9
By: Tamaru, T.; Nakamura, Y.; Kanai, M.; Kuroda, J.; Nakata, M.; Uemura, T.; Sugawara, Y.; Furukawa, R.; Yamamoto, S.; Kunitomo, M.; Asano, I.; Tadaki, Y.; Sekiguchi, T.; Ohji, Y.; Iijima, S.; Kisu, T.; Morino, M.; Nakamura, M.; Kawamura, H.; Kawakita, K.; Yamada, S.; Kawagoe, T.;
A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse
2001 / IEEE / 0-7803-6608-5
By: Kajigaya, K.; Kimura, K.; Nakamura, M.; Shukuri, S.; Yamada, S.; Arai, K.; Tadaki, Y.; Morino, M.; Miyatake, S.; Fujisawa, H.; Narui, S.; Takemura, R.; Sekiguchi, T.; Takahashi, T.; Itoh, K.;
A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuse
2001 / IEEE
By: Tadaki, Y.; Kajigaya, K.; Shukuri, S.; Yamada, S.; Arai, K.; Nakamura, M.; Morino, M.; Miyatake, S.; Fujisawa, H.; Narui, S.; Takemura, R.; Sekiguchi, T.; Takahashi, T.; Itoh, K.; Kimura, K.;
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
2002 / IEEE / 0-7803-7310-3
By: Morino, M.; Nakamura, M.; Narui, S.; Kubouchi, S.; Arai, K.; Fujisawa, H.; Takaishi, Y.; Sakito, Y.; Takahashi, T.; Takai, Y.; Matano, T.; Miyazawa, K.; Koyama, K.; Sekiguchi, T.; Miyatake, S.;
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
2003 / IEEE
By: Sakito, Y.; Fujii, I.; Takai, Y.; Matano, T.; Koyama, K.; Sekiguchi, T.; Miyatake, S.; Nakamura, M.; Morino, M.; Takahashi, T.; Arai, K.; Narui, S.; Kubouchi, S.; Fujisawa, H.; Takaishi, Y.;
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer
2004 / IEEE / 0-7803-8287-0
By: Usuki, N.; Dono, C.; Matano, T.; Narui, S.; Koshikawa, Y.; Takai, Y.; Nakamura, M.; Fujisawa, H.; Adachi, T.; Yoko, H.; Fujii, I.; Kubouchi, S.; Arai, K.; Morino, M.; Miyatake, S.;
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer
2005 / IEEE
By: Fujisawa, H.; Adachi, T.; Takai, Y.; Koshikawa, Y.; Matano, T.; Narui, S.; Usuki, N.; Dono, C.; Miyatake, S.; Morino, M.; Arai, K.; Kubouchi, S.; Fujii, I.; Yoko, H.; Nakamura, M.;
A Force/Displacement Transformation Method for Digitalized Virtual Deformable Object
2006 / IEEE / 1-4244-0341-3
By: Ogawa, N.; Morino, M.; Yoshida, H.; Noborio, H.;

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