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Author: Meindl, J.D.

Results

p-Type Electrical Transport of Chemically Doped Epitaxial Graphene Nanoribbons
2012 / IEEE
By: Bryan, S.E.; Brenner, K.; Yinxiao Yang; Murali, R.; Meindl, J.D.;
Offset word-line architecture for scaling DRAMs to the gigabit level
1988 / IEEE
By: Meindl, J.D.; Scheuerlein, R.E.;
An analytical two-dimensional model for silicon MESFETs
1988 / IEEE
By: Meindl, J.D.; Marshall, J.D.;
A sub- and near-threshold current model for silicon MESFETs
1988 / IEEE
By: Marshall, J.D.; Meindl, J.D.;
A novel technique for detecting lithographic defects
1988 / IEEE
By: McCarthy, A.M.; Meindl, J.D.; Dameron, D.H.; Fu, C.C.; Lukaszek, W.;
A process for the combined fabrication of ion sensors and CMOS circuits
1988 / IEEE
By: Shott, J.; Bousse, L.; Meindl, J.D.;
MOSFET scaling limits determined by subthreshold conduction
1989 / IEEE
By: Pimbley, J.M.; Meindl, J.D.;
Analytic analysis of 77 K CMOS minimum channel length
1989 / IEEE
By: Abramczyk, E.R.; Meindl, J.D.;
A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy
1990 / IEEE
By: Meindl, J.D.; Varshney, R.C.; Michalka, T.L.;
A redundant metal-polyimide thin film interconnection process for wafer scale dimensions
1990 / IEEE
By: Meindl, J.D.; Lukaszek, W.; Michalka, T.L.;
Three-region analytical models for MESFETs in low-voltage digital circuits
1991 / IEEE
By: Meindl, J.D.; De, V.K.;
An implantable multichannel ultrasonic pulsed Doppler blood flowmeter
1989 / IEEE
By: Sebek, J.J.; Yeung, K.-W.W.; Meindl, J.D.;
Gigascale integration (GIS) in the 21st century
1991 / IEEE / 0-8186-2270-9
By: Meindl, J.D.;
An analytical threshold voltage and subthreshold current model for short-channel MESFETs
1993 / IEEE
By: De, V.K.; Meindl, J.D.;
An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETs
1993 / IEEE
By: De, V.K.; Meindl, J.D.;
Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conduction
1993 / IEEE
By: De, V.K.; Meindl, J.D.;
Gigascale integration (GSI) beyond 2001
1991 / IEEE / 0-7803-0036-X
By: Meindl, J.D.;
A prospectus for gigascale integration (GSI)
1993 / IEEE / 0-7803-1212-0
By: Meindl, J.D.;
Short channel models and scaling limits of SOI and bulk MOSFETs
1994 / IEEE
By: Pimbley, J.M.; De, V.K.; Agrawal, B.; Meindl, J.D.;
Prospects of gigascale integration (GSI) beyond 2003
1993 / IEEE / 0-7803-0987-1
By: Agrawal, B.; De, V.K.; Meindl, J.D.;
A physical model including velocity overshoot for drain current of sub-0.15 /spl mu/m MOSFET's
1993 / IEEE / 0-7803-1450-6
By: Meindl, J.D.; Agrawal, B.; De, V.K.;
Low power microelectronics: retrospect and prospect
1995 / IEEE
By: Meindl, J.D.;
Three-dimensional analytical subthreshold models for bulk MOSFETs
1995 / IEEE
By: Meindl, J.D.; De, V.K.; Agrawal, B.;
Device parameter optimization for reduced short channel effects in retrograde doping MOSFET's
1996 / IEEE
By: Meindl, J.D.; De, V.K.; Agrawal, B.;
Complementary adiabatic and fully adiabatic MOS logic families for gigascale integration
1996 / IEEE / 0-7803-3136-2
By: De, V.K.; Meindl, J.D.;
Random MOSFET parameter fluctuation limits to gigascale integration (GSI)
1996 / IEEE / 0-7803-3342-X
By: Meindl, J.D.; Xinghai Tang; De, V.K.;
A first generation generic system simulator (GENESYS) and its relation to the NTRS
1995 / IEEE / 0-7803-2596-6
By: Meindl, J.D.; De, V.K.; Eble, J.C.;
21st century gigascale integration (GSI)
1995 / IEEE / 0-7803-2467-6
By: Meindl, J.D.;
Gigascale integration: is the sky the limit?
1996 / IEEE
By: Meindl, J.D.;
Scaling limits of Si MOSFET technology imposed by random parameter fluctuations
1996 / IEEE / 0-7803-3358-6
By: Xinghai Tang; De, V.K.; Meindl, J.D.;
Effects of random MOSFET parameter fluctuations on total power consumption
1996 / IEEE / 0-7803-3571-6
By: Xinghai Tang; Meindl, J.D.; De, V.K.;
A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)
1996 / IEEE / 0-7803-3571-6
By: Meindl, J.D.; De, V.K.;
A priori wiring estimations and optimal multilevel wiring networks for portable ULSI systems
1996 / IEEE / 0-7803-3286-5
By: De, V.K.; Davis, J.A.; Meindl, J.D.;
A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001
1996 / IEEE / 0-7803-3302-0
By: Eble, J.C.; Meindl, J.D.; Wills, D.S.; De, V.K.;
Opportunities for non-dissipative computation [adiabatic logic]
1996 / IEEE / 0-7803-3302-0
By: Meindl, J.D.; De, V.K.;
Optimal circuit design for low power CMOS GSI
1996 / IEEE / 0-7803-3302-0
By: Bhavnagarwala, A.J.; Meindl, J.D.; Austin, B.; De, V.K.;
The impact of stochastic dopant and interconnect distributions on gigascale integration
1997 / IEEE / 0-7803-3721-2
By: Bhavnagarwala, A.J.; Austin, B.; Davis, J.A.; Xinghai Tang; Eble, J.C.; Wills, D.S.; De, V.K.; Meindl, J.D.;
A stochastic wire length distribution for gigascale integration (GSI)
1997 / IEEE / 0-7803-3669-0
By: De, V.K.; Davis, J.A.; Meindl, J.D.;
Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010
1997 / IEEE / 0-7803-4283-6
By: Meindl, J.D.; Austin, B.; Bhavnagarwala, A.J.;
A history of low power electronics: how it began and where it's headed
1997 / IEEE / 0-89791-903-3
By: Meindl, J.D.;
Intrinsic MOSFET parameter fluctuations due to random dopant placement
1997 / IEEE
By: Meindl, J.D.; De, V.K.; Xinghai Tang;
A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation
1998 / IEEE
By: De, V.K.; Davis, J.A.; Meindl, J.D.;
A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation
1998 / IEEE
By: Meindl, J.D.; De, V.K.; Davis, J.A.;
An Asynchronous Digital Multiplexer For Biotelemetry
1988 / IEEE
By: Shott, J.D.; Shapiro, F.B.; Meindl, J.D.;
Is interconnect the weak link?
1998 / IEEE
By: Davis, J.A.; Meindl, J.D.;
Opportunities for Gigascale Integration (GSI) Beyond 2003
1993 / IEEE
By: Meindl, J.D.;
Stochastic net length distributions for global interconnects in a heterogeneous system-on-a-chip
1998 / IEEE / 0-7803-4770-6
By: Zarkesh-Ha, P.; Meindl, J.D.;
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule
1998 / IEEE / 0-7803-4292-5
By: Davis, J.A.; Zarkesh-Ha, P.; Meindl, J.D.; Loh, W.;
Minimum repeater count, size, and energy dissipation for gigascale integration (GSI) interconnects
1998 / IEEE / 0-7803-4285-2
By: Wills, D.S.; De, V.K.; Eble, J.C.; Meindl, J.D.;
Stochastic interconnect network fan-out distribution using Rent's rule
1998 / IEEE / 0-7803-4285-2
By: Loh, W.; Davis, J.A.; Zarkesh-Ha, P.; Meindl, J.D.;
Minimum supply voltage for bulk Si CMOS GSI
1998 / IEEE / 1-58113-059-7
By: Meindl, J.D.; Austin, B.; Bhavnagarwala, A.J.;
A low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI)
1998 / IEEE / 0-7803-4980-6
By: Austin, B.L.; Meindl, J.D.; Xinghai Tang; Bowman, K.A.;
Threshold voltage roll-off model for low power bulk accumulation MOSFETs
1998 / IEEE / 0-7803-4980-6
By: Meindl, J.D.; Tang, X.; Austin, B.L.; Richards, W.R.; Dennen, M.;
XXI century gigascale integration (GSI): the interconnect problem
1999 / IEEE / 0-7695-0056-0
By: Meindl, J.D.;
Characterization and modeling of clock skew with process variations
1999 / IEEE / 0-7803-5443-5
By: Mule, T.; Zarkesh-Ha, P.; Meindl, J.D.;
Optimum chip clock distribution networks
1999 / IEEE / 0-7803-5174-6
By: Meindl, J.D.; Zarkesh-Ha, P.;
Length, scaling, and material dependence of crosstalk between distributed RC interconnects
1999 / IEEE / 0-7803-5174-6
By: Davis, J.A.; Meindl, J.D.;
A physical alpha-power law MOSFET model
1999 / IEEE
By: Xinghai Tang; Eble, J.C.; Austin, B.L.; Bowman, K.A.; Meindl, J.D.;
Compact distributed RLC models for multilevel interconnect networks
1999 / IEEE / 4-930813-95-6
By: Meindl, J.D.; Davis, J.A.;
Compact distributed RLC models for multilevel interconnect networks
1999 / IEEE / 4-930813-93-X
By: Meindl, J.D.; Davis, J.A.;
A physical alpha-power law MOSFET model
1999 / IEEE / 1-58113-133-X
By: Eble, J.C.; Austin, B.L.; Bowman, K.A.; Meindl, J.D.; Tang, X.;
Performance enhancement through optimal n-tier multilevel interconnect architectures
1999 / IEEE / 0-7803-5632-2
By: Davis, J.A.; Venkatesan, R.; Meindl, J.D.;
The impact of Cu/low /spl kappa/ on chip performance
1999 / IEEE / 0-7803-5632-2
By: Zarkesh-Ha, P.; Meindl, J.D.; JinJoo Lee; Loh, W.; Bendix, P.;
Impact of extrinsic and intrinsic parameter variations on CMOS system on a chip performance
1999 / IEEE / 0-7803-5632-2
By: Bowman, K.A.; Meindl, J.D.; Eble, J.C.; Xinghai Tang;
A 10 GHz hybrid optical/electrical clock distribution network for gigascale integration
1999 / IEEE / 0-7803-5634-9
By: Gaylord, T.K.; Schultz, S.M.; Mule, A.V.; Meindl, J.D.;
Interconnect limits on gigascale integration
1999 / IEEE / 0-7803-5597-0
By: Meindl, J.D.;
Asymptotically zero power dissipation gigahertz clock distribution networks
1999 / IEEE / 0-7803-5597-0
By: Payman Zarkesh-Ha; Meindl, J.D.;
SOI MOSFET fluctuation limits on gigascale integration (GSI)
1999 / IEEE / 0-7803-5456-7
By: De, V.K.; Xinghai Tang; Meindl, J.D.; Lihui Wang;
A minimum total power methodology for projecting limits on CMOS GSI
2000 / IEEE
By: Bhavnagarwala, A.J.; Meindl, J.D.; Bowman, K.A.; Austin, B.L.;
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)
2000 / IEEE / 0-7803-6305-1
By: Zarkesh-Ha, P.; Meindl, J.D.;
Cost analysis of compliant wafer level package
2000 / IEEE / 0-7803-5908-9
By: Patel, C.S.; Meindl, J.D.; Martin, K.; Power, C.; Merriweather, S.; Realff, M.;
An optical clock distribution network for gigascale integration
2000 / IEEE / 0-7803-6327-2
By: Schultz, S.M.; Mule, A.V.; Meindl, J.D.; Gaylord, T.K.;
A novel via blockage model and its implications
2000 / IEEE / 0-7803-6327-2
By: Qiang Chen; Meindl, J.D.; Payman Zarkesh-Ha; Davis, J.A.;
A three-dimensional stochastic wire-length distribution for variable separation of strata
2000 / IEEE / 0-7803-6327-2
By: Meindl, J.D.; Davis, J.A.; Zarkesh-Ha, P.; Joyner, J.W.;
Generic models for interconnect delay across arbitrary wire-tree networks
2000 / IEEE / 0-7803-6327-2
By: Kapoor, A.; Bhavnagarwala, A.J.; Meindl, J.D.;
Optimal repeater insertion for n-tier multilevel interconnect architectures
2000 / IEEE / 0-7803-6327-2
By: Bowman, K.A.; Davis, J.A.; Venkatesan, R.; Meindl, J.D.;
Impact of interconnect parameter variations on wire-tree delay
2000 / IEEE / 0-7803-5896-1
By: Meindl, J.D.; Kapoor, A.; Bhavnagarwala, A.J.;
The fundamental limit on binary switching energy for terascale integration (TSI)
2000 / IEEE
By: Davis, J.A.; Meindl, J.D.;
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion
2000 / IEEE / 1-58113-190-9
By: Davis, J.A.; Venkatesan, R.; Meindl, J.D.; Bowman, K.A.;
Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions
2000 / IEEE
By: Davis, J.A.; Meindl, J.D.;
Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks
2000 / IEEE
By: Meindl, J.D.; Davis, J.A.;
Dynamic-threshold CMOS SRAM cells for fast, portable applications
2000 / IEEE / 0-7803-6598-4
By: Bhavnagarwala, A.J.; Meindl, J.D.; Kapoor, A.;
Performance improvement using on-board wires for on-chip interconnects
2000 / IEEE / 0-7803-6450-3
By: Zarkesh-Ha, P.; Naeemi, A.; Meindl, J.D.; Patel, C.S.;
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
2000 / IEEE
By: Meindl, J.D.; Davis, J.A.; Zarkesh-Ha, P.;
Heterogeneous architecture models for interconnect-motivated system design
2000 / IEEE
By: Taha, T.M.; Sek Meng Chai; Meindl, J.D.; Wills, D.S.;
A compact physical via blockage model
2000 / IEEE
By: Meindl, J.D.; Zarkesh-Ha, P.; Davis, J.A.; Qiang Chen;
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution
2001 / IEEE / 0-7803-6608-5
By: Bowman, K.A.; Meindl, J.D.; Duvall, S.G.;
Sea of leads: a disruptive paradigm for a system-on-a-chip (SoC)
2001 / IEEE / 0-7803-6608-5
By: Bakir, M.S.; Patel, G.S.; Naeemi, A.; Meindl, J.D.; Martin, K.P.; Zarkesh-Ha, P.;
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
2001 / IEEE
By: Meindl, J.D.; Xinghai Tang; Bhavnagarwala, A.J.;
Interconnect limits on gigascale integration (GSI) in the 21st century
2001 / IEEE
By: Banerjee, K.; Souri, S.J.; Venkatesan, R.; Beylansky, M.; Kaloyeros, A.; Saraswat, K.C.; Davis, J.A.; Meindl, J.D.; Reif, R.; Rahman, A.;
Advanced interconnect technology
2000 / IEEE / 964-360-057-2
By: Meindl, J.D.;
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)
2000 / IEEE / 964-360-057-2
By: Zarkesh-Ha, P.; Meindl, J.D.;
Electrical test strategies for a wafer-level batch packaging technology
2001 / IEEE / 0-7803-7038-4
By: Patel, C.S.; Keezer, D.C.; Meindl, J.D.; Zhou, Q.;
Electrical performance of compliant wafer level package
2001 / IEEE / 0-7803-7038-4
By: Meindl, J.D.; Martin, K.; Patel, C.S.;
Impact of within-die parameter fluctuations on future maximum clock frequency distributions
2001 / IEEE / 0-7803-6591-7
By: Meindl, J.D.; Bowman, K.A.;
A model for interlevel coupling noise in multilevel interconnect structures
2001 / IEEE / 0-7803-6678-6
By: Swaminathan, M.; Ajmal, Z.; Saint-Laurent, M.; Meindl, J.D.;
Optimum on-chip power distribution networks for gigascale integration (GSI)
2001 / IEEE / 0-7803-6678-6
By: Zarkesh-Ha, P.; Meindl, J.D.;
Input coupling and guided-wave distribution schemes for board-level intra-chip guided-wave optical clock distribution network using volume grating coupler technology
2001 / IEEE / 0-7803-6678-6
By: Glytsis, E.N.; Schultz, S.M.; Mule, A.V.; Meindl, J.D.; Gaylord, T.K.;
An optimal partition between on-chip and on-board interconnects
2001 / IEEE / 0-7803-6678-6
By: Meindl, J.D.; Naeemi, A.;
Compliant wafer level package (CWLP) with embedded air-gaps for sea of leads (SoL) interconnections
2001 / IEEE / 0-7803-6678-6
By: Kohl, P.A.; Meindl, J.D.; Martin, K.P.; Patel, C.S.; Bakir, M.S.; Reed, H.A.;

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