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Author: Malhi, S.D.S.

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A low-voltage micropower JFET/bipolar operational amplifier
1981 / IEEE
By: Malhi, S.D.S.; Donnison, W.R.; Salama, C.A.T.;
Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon
1985 / IEEE
By: Sundaresan, R.; Chatterjiee, P.K.; Banerjee, S.K.; Shichijo, H.; Malhi, S.D.S.; Hon Wai Lam; Elahy, M.; Womack, R.H.; Hite, L.R.; Shah, A.H.; Richardson, W.F.; Pollack, G.P.;
A 4-Mbit DRAM with trench-transistor cell
1986 / IEEE
By: Wang, C.; Womack, R.H.; Shah, A.H.; Chatterjee, P.K.; Tran, B.; Pilch, C.J.; Malhi, S.D.S.; Bordelon, D.M.; Richardson, W.F.; Pollack, G.P.; Banerjee, S.K.; Elahy, M.; Davis, H.E.; Shichijo, H.; Gallia, J.D.;
Subsurface junction field effect transistor (SJFET)
1980 / IEEE
By: Malhi, S.D.S.; Barber, H.D.; Donnison, W.; Salama, C.A.T.;
Subsurface junction field effect transistor
1981 / IEEE
By: Malhi, S.D.S.; Salama, C.A.T.; Donnison, W.R.; Barber, H.D.;
Novel SOI CMOS design using ultra thin near intrinsic substrate
1982 / IEEE
By: Hamdi, A.H.; Pinizzotto, R.F.; Lam, H.W.; Malhi, S.D.S.; McDaniel, F.D.;
SOI CMOS circuit performance on graphite strip heater recrystallized material
1982 / IEEE
By: Pinizzotto, R.F.; Lam, H.W.; Malhi, S.D.S.;
VB-1 characteristics of p-channel MOSFETs in LPCVD polysilicon and effect of grain boundary passivation on device performance
1983 / IEEE
By: Malhi, S.D.S.; Shah, R.R.; Chatterjee, P.K.; Lam, H.W.; Pinizzoto, R.F.; Chen, C.E.C.; Bellavance, D.W.; Shichijo, H.;
VB-3 stacked CMOS sRAM cell
1983 / IEEE
By: Chen, C.-E.; Lam, H.W.; Malhi, S.D.S.; Pinizzotto, R.F.;
Stacked CMOS SRAM cell
1983 / IEEE
By: Malhi, S.D.S.; Lam, H.W.; Chen, C.-E.; Pinizzotto, R.F.;
p-Channel MOSFET's in LPCVD PolySilicon
1983 / IEEE
By: Pinizzotto, R.F.; Bellavance, D.W.; Chatterjee, P.K.; Malhi, S.D.S.; Lam, H.W.; Shah, R.R.; Shichijo, H.; Chen, C.E.C.;
Characterization of n-channel and p-channel LPCVD polysilicon MOSFETs
1983 / IEEE
By: Chatterjee, P.K.; Malhi, S.D.S.; Shichijo, H.; Lam, H.W.; Douglas, M.A.; Shah, R.R.;
VB-1 a VLSI suitable 2-µm stacked CMOS process
1984 / IEEE
By: Malhi, S.D.S.; Karnaugh, R.; Hester, R.K.; Pinizzotto, R.F.; Haken, R.A.; Shah, A.H.; Hite, L.; Chatterjee, P.K.; Davis, H.E.; Mahant-Shetti, S.S.; Gosmeyer, C.D.; Sundaresan, R.S.; Chen, C.E.; Lam, H.W.;
VB-5 comparison of accumulation and inversion mode LPCVD polysilicon MOSFET characteristics for memory applications
1984 / IEEE
By: Banerjee, S.K.; Elahy, M.; Shichijo, H.; Pollack, G.P.; Richardson, W.F.; Malhi, S.D.S.; Shah, A.H.; Womack, R.H.; Lam, H.W.; Chatterjee, P.K.;
Edge-defined self-alignment of submicrometer overlaid devices
1984 / IEEE
By: Leiss, J.E.; Bonifield, T.D.; Chatterjee, P.K.; Malhi, S.D.S.; Coleman, D.J.; Pinizzotto, R.F.; Carter, D.E.;
Hydrogen passivation of PolySilicon MOSFET's from a plasma Nitride source
1984 / IEEE
By: Elahy, M.; Pollack, G.P.; Chatterjee, P.K.; Womack, R.; Shah, A.H.; Richardson, W.F.; Banerjee, S.; Shichijo, H.; Bonifield, T.; Malhi, S.D.S.;
Polysilicon transistors in VLSI MOS memories
1984 / IEEE
By: Shichijo, H.; Malhi, S.D.S.; Chatterjee, P.K.; Lam, H.W.; Womack, R.H.; Sundaresan, R.; Elahy, M.; Banerjee, S.K.; Hite, L.R.; Shah, A.H.; Pollack, G.P.; Richardson, W.F.;
SOI-CMOS 4K SRAM with high dose oxygen implanted substrate
1984 / IEEE
By: Hite, L.R.; Blake, T.G.W.; Chen, C.-E.; Lam, H.W.; Mao, B.-Y.; Malhi, S.D.S.;
A fully self-aligned stacked CMOS 64K SRAM
1984 / IEEE
By: Hite, L.R.; Malhi, S.D.S.; Sundaresan, R.; Chatterjee, P.K.; Lam, H.W.; Shah, A.H.;
Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon
1985 / IEEE
By: Malhi, S.D.S.; Shichijo, H.; Lam, H.W.; Chatterjee, P.K.; Womack, R.H.; Banerjee, S.K.; Sundaresan, R.; Elahy, M.; Pollack, G.P.; Richardson, W.F.; Shah, A.H.; Hite, L.R.;
Process and performance comparison of an 8K × 8-bit SRAM in three stacked CMOS technologies
1985 / IEEE
By: Lam, H.W.; Malhi, S.D.S.; Sundaresan, R.; Hite, L.R.; Chatterjee, P.K.; Hester, R.K.; Shah, A.H.;
A trench transistor cross-point DRAM cell
1985 / IEEE
By: Richardson, W.F.; Bordelon, D.M.; Chatterjee, P.K.; Davis, H.E.; Gallia, J.; Wang, C.-P.; Womack, R.H.; Elahy, M.; Banerjee, S.K.; Shichijo, H.; Malhi, S.D.S.; Shah, A.H.; Pollack, G.P.;
Trench transistor DRAM cell
1986 / IEEE
By: Shichijo, H.; Banerjee, S.K.; Chatterjee, P.K.; Shah, A.H.; Davis, H.E.; Gallia, J.; Wang, C.-P.; Elahy, M.; Womack, R.H.; Bordelon, D.M.; Richardson, W.F.; Pollack, G.P.; Malhi, S.D.S.;
Orthogonal chip mount - A 3D hybrid wafer scale integration technology
1987 / IEEE
By: Stierman, R.J.; Davis, H.E.; Malhi, S.D.S.; Chatterjee, P.K.; Driscoll, C.C.; Bean, K.E.;

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