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Author: Lindsay, R.

Results

Relevance-Derived Metafunction: How to Interface Intelligent System's Sub-Components

1992 / IEEE / 0-8186-2675-5
By: Marsh, J.; Cox, K.R.; Lindsay, R.; Gorayska, B.; Tse, N.;

Progress Tones in PCM Switching Environment

1973 / IEEE
By: Pitroda, S.; Lindsay, R.;

A practical baseline process for advanced CMOS devices research [sub-50 nm MOSFETs]

2003 / IEEE / 0-7803-7999-3
By: Surdeanu, R.; Doornbos, G.; Hooker, J.C.; Lander, R.J.P.; Rittersma, Z.M.; Loo, J.J.G.P.; Cubaynes, F.N.; Ponomarev, Y.V.; Lindsay, R.; Henson, K.; Kubicek, S.; Dachs, C.J.J.;

Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node

2002 / IEEE / 0-7803-7155-0
By: Pages, X.; Maex, K.; Stolk, P.; Surdeanu, R.; Lindsay, R.; Pawlak, B.;

SPER junction optimisation in 45 nm CMOS devices

2004 / IEEE / 0-7803-8191-2
By: Henson, K.; Maex, K.; Pawlak, B.J.; Severi, S.; Lindsay, R.; Lauwers, A.; Lendzian, H.; Surdeanu, R.; Satta, A.; Pages, X.;

Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line

2004 / IEEE / 0-7803-8478-4
By: De Jaeger, B.; Heyns, M.; Satta, A.; Kubicek, S.; Verheyen, P.; Van Steenbergen, J.; Croon, J.; Kaczer, B.; Van Elshocht, S.; Delabie, A.; Kunnen, E.; Sleeckx, E.; Teerlinck, I.; Lindsay, R.; Schram, T.; Chiarella, T.; Degraeve, R.; Conard, T.; Poortmans, J.; Winderickx, G.; Boullart, W.; Schaekers, M.; Mertens, P.W.; Caymax, M.; Vandervorst, W.; Van Moorhem, E.; Biesemans, S.; De Meyer, K.; Ragnarsson, L.; Lee, S.; Kota, G.; Raskin, G.; Mijlemans, P.; Autran, J.-L.; Afanas'ev, V.; Stesmans, A.; Meuris, M.; Houssa, M.;

Channel engineering towards a full low temperature process solution for the 45 nm technology node [NMOS transistors]

2004 / IEEE / 0-7803-8478-4
By: De Meyer, K.; Pawlak, B.J.; Lindsay, R.; Henson, K.; Severi, S.;

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

2004 / IEEE / 0-7803-8684-1
By: Vandervost, W.; Jurczak, M.; Ramos, J.; de Marneffe, J.F.; Eyben, P.; Veloso, A.; Lauwers, A.; Henson, K.; Anil, K.G.; Severi, S.; Dachs, C.; Camillo-Castillo, R.A.; Lindsay, R.; Duffy, R.; Pawlak, J.B.; De Meyer, K.; Biesemans, S.;

Elevated Co-Silicide for sub-100nm High Performance and RF CMOS

2002 / IEEE / 88-900847-8-2
By: Jurczak, M.; de Potter, M.; Rooyackers, R.; Jeamsaksiri, W.; Redolfi, A.; Grau, L.; Lauwers, A.; Badenes, G.; Augendre, E.; Lindsay, R.; Peytier, I.;

Design of high performance PFETs with strained si channel and laser anneal

2005 / IEEE / 0-7803-9268-X
By: Luo, Z.; Rim, K.; Ng, H.; Schepis, D.; Amos, R.; Mishra, S.; Lee, J.; Ajmera, A.; Lindsay, R.; Gluschenkov, O.; Turansky, A.; Madan, A.; Davis, R.; Li, J.; Chidambarrao, D.; Holt, J.; Sato, T.; Panda, S.; Greene, B.; Rovedo, N.; Kim, J.; Chong, Y.F.;

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

2006 / IEEE / 1-4244-0005-8
By: Yuan, J.; Schiml, T.; Hierlemann, M.; Ku, J.; Sudijono, J.; Ng, K.; Barton, K.; Li, J.; Yang, Z.; Stierstorfer, R.; Rovedo, N.; Dyer, T.; Fang, S.; Lee, W.; Luo, Z.; Amos, R.; Hook, T.; Sardesai, V.; Lindsay, R.; Kim, J.; Lee, Y.M.; Tan, S.S.;

Arsenic Junction Thermal Stability and High-Dose Boron-Pocket Activation During SPER in nMOS Transistors

2007 / IEEE
By: De Meyer, K.; Lindsay, R.; Henson, K.; Augendre, E.; Duffy, R.; Pawlak, B.J.; Severi, S.;

Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices

2006 / IEEE / 1-4244-0438-X
By: Han, J.P.; Utomo, H.; Ieong, M.; Sudijono, J.; Ku, J.H.; Shum, D.; Hierlemann, M.; Amos, R.; Chiulli, G.; Lindsay, R.; Kim, S.D.; Loesing, R.; Burns, L.; Turansky, A.; Madan, A.; St Lawrence, B.; Davis, R.; Murphy, R.; Li, J.; Li, J.; Kim, J.J.; Zhuang, H.; Mishra, S.; Schepis, D.; Gutmann, A.; Teo, L.W.; Rovedo, N.; Luo, Z.; Krishnasamy, R.; Stierstorfer, R.; Chong, Y.F.; Fang, S.; Ng, H.; Holt, J.; Adam, T.N.; Kempisty, J.;

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

2007 / IEEE
By: Galiano, M.; Jaiswal, R.; Wille, W.; Conti, R.; Lindsay, R.; Jain, A.; Bach, K.-H.; Eller, M.; Stapelmann, C.; Tilke, A.T.; Hampp, R.;

Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology

2007 / IEEE / 978-1-4244-1771-9
By: Hyotae Choo; Sungjoon Park; Lindsay, R.; Chu-Hsin Liang; Huiling Shang; Chan, V.; Jae-Eun Park; Jun Yuan; Hook, T.; Ahlgren, D.; Enhai Zhao; Jing Wang; Xiaobin Yuan;

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

2008 / IEEE / 978-1-4244-1802-2
By: Chen, X.; Samavedam, S.; Narayanan, V.; Stein, K.; Hobbs, C.; Baiocco, C.; Li, W.; Jaeger, D.; Zaleski, M.; Yang, H.S.; Kim, N.; Lee, Y.; Zhang, D.; Kang, L.; Chen, J.; Zhuang, H.; Sheikh, A.; Wallner, J.; Aquilino, M.; Han, J.; Jin, Z.; Li, J.; Massey, G.; Kalpat, S.; Jha, R.; Moumen, N.; Mo, R.; Kirshnan, S.; Wang, X.; Chudzik, M.; Chowdhury, M.; Nair, D.; Reddy, C.; Teh, Y.W.; Kothandaraman, C.; Coolbaugh, D.; Pandey, S.; Tekleab, D.; Thean, A.; Sherony, M.; Lage, C.; Sudijono, J.; Lindsay, R.; Ku, J.H.; Khare, M.; Steegen, A.;

Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology

2008 / IEEE
By: Hook, T.; Ahlgren, D.C.; Enhai Zhao; Jing Wang; Jae-Eun Park; Xiaobin Yuan; Jun Yuan; Sungjoon Park; Lindsay, R.; Hyotae Choo; Chu-Hsin Liang; Huiling Shang; Chan, V.;

High-�/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond

2009 / IEEE / 978-1-4244-2784-0
By: Park, D.-G.; Stein, K.; Khare, M.; Divakaruni, R.; Steegen, A.; Lindsay, R.; Sherony, M.; Narayanan, V.; Samavedam, S.; Theon, V.-Y.; Chudzik, M.; Schepis, D.; Haetty, J.; Chowdhury, M.; Kanarsky, T.; Yan, W.; Chen, J.; Zhuang, H.; Jaeger, D.; Chen, X.; Loesing, R.; Tang, T.; Hatzistergos, M.; Moumen, N.; von Arnim, K.; Han, S.; Schruefer, K.; Lee, Y.; Han, J.-P.; Li, W.; Yin, H.; Pacha, C.; Kim, N.; Ostermayr, M.; Eller, M.; Kim, S.; Kim, K.;

Competitive and cost effective high-k based 28nm CMOS technology for low power applications

2009 / IEEE / 978-1-4244-5641-3
By: Arnaud, F.; Sampson, R.; Eller, M.; Lipinski, M.; Teh, Y.W.; Ostermayr, M.; Kang, K.; Kim, N.S.; Ohuchi, K.; Han, J.-P.; Nair, D.R.; Lian, J.; Uchimura, S.; Kohler, S.; Miyaki, S.; Ferreira, P.; Park, J.-H.; Hamaguchi, M.; Miyashita, K.; Augur, R.; Zhang, Q.; Strahrenberg, K.; ElGhouli, S.; Bonnouvrier, J.; Matsuoka, F.; Lindsay, R.; Sudijono, J.; Johnson, F.S.; Ku, J.H.; Sekine, M.; Steegen, A.; Thean, A.;

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