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Author: Leobandung, E.

Results

Sub-25nm FinFET with advanced fin formation and short channel effect engineering
2011 / IEEE / 978-1-4244-9949-6
By: Yamashita, T.; Basker, V.S.; Standaert, T.; Yeh, C.-C.; Yamamoto, T.; Maitra, K.; Lin, C.-H.; Faltermeier, J.; Kanakasabapathy, S.; Wang, M.; Sunamura, H.; Jagannathan, H.; Reznicek, A.; Schmitz, S.; Inada, A.; Wang, J.; Adhikari, H.; Berliner, N.; Lee, K.-L.; Kulkarni, P.; Zhu, Y.; Kumar, A.; Bryant, A.; Wu, S.; Kanarsky, T.; Cho, J.; Mclellan, E.; Holmes, S.J.; Johnson, R.C.; Levin, T.; Demarest, J.; Li, J.; Oldiges, P.; Arnold, J.; Colburn, M.; Hane, M.; Mcherron, D.; Paruchuri, V.K.; Doris, B.; Miller, R.J.; Bu, H.; Khare, M.; O'Neill, J.; Leobandung, E.;
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
2011 / IEEE / 978-1-4244-9949-6
By: Hailing Wang; Leobandung, E.; Oldiges, P.; Haensch, W.; Chung-Hsun Lin; Khare, M.; Williams, R.; Bu, H.; Standaert, T.; Yamashita, T.; Bryant, A.; Guillorn, M.; Chang, J.;
Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty
2012 / IEEE / 978-1-4673-0847-2
By: Leobandung, E.; Park, D.; Cheng, K.; Frank, D.J.; Yamaoka, M.; Miki, H.; Torii, K.;
A Four-FET Method for Extracting Mobility in FETs Without Field Oxide
2014 / IEEE
By: Sadana, D.K.; Shiu, K.; Cheng, C.; Lee, K.; Majumdar, A.; Leobandung, E.;
CMOS-Compatible Self-Aligned In0.53Ga0.47As MOSFETs With Gate Lengths Down to 30 nm
2014 / IEEE
By: Majumdar, A.; Sun, Y.; Leobandung, E.; Park, D.; Sadana, D.K.; Duch, E.A.; Kobayashi, M.; Cheng, S.; Frank, M.M.; de Souza, J.P.; Cheng, C.; Kim, Y.; Rana, U.; Martin, R.M.; Bruce, R.L.; Shiu, K.; Zhu, Y.; Farmer, D.B.; Hopstaken, M.; Joseph, E.A.;
Threshold voltage sensitivity of 0.1 /spl mu/m channel length fully-depleted SOI NMOSFET's with back-gate bias
1995 / IEEE
By: Chou, S.Y.; Leobandung, E.;
Silicon quantum-dot transistors operating above 100 K
1995 / IEEE / 0-7803-2788-8
By: Lingjie Guo; Leobandung, E.; Chou, S.Y.; Yun Wang;
Silicon single hole quantum dot transistors for complementary digital circuits
1995 / IEEE / 0-7803-2700-4
By: Lingjie Guo; Leobandung, E.; Chou, S.Y.;
Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length
1996 / IEEE / 0-7803-3358-6
By: Chou, S.Y.; Leobandung, E.;
Si single-electron MOS memory with nanoscale floating-gate and narrow channel
1996 / IEEE / 0-7803-3393-4
By: Chou, S.Y.; Leobandung, E.; Langjie Guo;
A 7.9/5.5 psec room/low temperature SOI CMOS
1997 / IEEE / 0-7803-4100-7
By: Leobandung, E.; Shahidi, G.; Ajmera, A.; Rausch, W.; Assaderaghi, F.; Schepis, D.; Davari, B.; Yee, D.; Bolam, R.; Wann, H.-J.; Wagner, L.;
A 0.25 /spl mu/m CMOS SOI technology and its application to 4 Mb SRAM
1997 / IEEE / 0-7803-4100-7
By: Ajmera, A.C.; Leobandung, E.; Bolam, R.J.; Rausch, W.; Yee, D.S.; Assaderaghi, F.; Schepis, D.J.; Shahidi, G.G.; Davari, B.; Chu, S.F.; Hakey, M.; Badami, D.A.; Fitzpatrick, D.; Martino, R.M.; Tallman, K.A.; Hsieh, M.C.; Kuang, J.B.; Ratanaphanyarat, S.; Saccamango, M.J.; Wagner, L.F.; Wu, S.; Schiller, C.; Kebede, T.; Hovel, H.J.; Sadana, D.; Flaker, R.; Kulkarni, S.B.;
Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation
1998 / IEEE / 0-7803-4774-9
By: Ajmera, A.; Schepis, D.; Wu, S.; Bolam, R.; Assaderaghi, F.; Rausch, W.; Sleight, J.; Sherony, M.; Leobandung, E.; Shahidi, G.; Davari, B.;
Partially-depleted SOI technology for digital logic
1999 / IEEE / 0-7803-5126-6
By: Assaderaghi, F.; Ajmera, A.; Shahidi, G.G.; Davari, B.; Kun Wu; Bolam, R.J.; Wagner, L.F.; Schepis, D.; Sankus, D.; Rausch, W.; Leobandung, E.;
Device and circuit design issues in SOI technology
1999 / IEEE / 0-7803-5443-5
By: Hovel, H.; Bolam, R.J.; Davari, B.; Assaderaghi, F.; Ajmera, A.; Shahidi, G.G.; Leobandung, E.; Wu, K.; Wissel, L.; Wagner, L.F.; Schepis, D.; Sadana, D.; Rausch, W.;
A 0.22 /spl mu/m CMOS-SOI technology with a Cu BEOL
1999 / IEEE / 4-930813-93-X
By: Coffey, M.; Hovel, H.; Bolam, R.; Assaderaghi, F.; Sleight, J.W.; Ajmera, A.; Shahidi, G.; Davari, B.; Wu, K.; Wagner, L.F.; Bryant, A.; Schepis, D.; Sadana, D.; Rausch, W.; Leobandung, E.; Lasky, J.;
Mainstreaming of the SOI technology
1999 / IEEE / 0-7803-5456-7
By: Bolam, R.; Sherony, M.; Assaderaghi, F.; Ajmera, A.; Shahidi, G.; Chen, T.C.; Davari, B.; Wu, K.; Wagner, L.F.; Sleight, J.W.; Bryant, A.; Schepis, D.; Sadana, D.; Rausch, W.; Moy, D.; Maloney, M.; Lo, H.-S.; Leobandung, E.; Lasky, J.; Hovel, H.; Coffey, M.;
High performance 0.18 /spl mu/m SOI CMOS technology
1999 / IEEE / 0-7803-5410-9
By: Sadana, D.; Schepis, D.; Chu, W.; Khare, M.; Schulz, R.; Lo, S.-H.; Sherony, M.; Barth, E.; Leobandung, E.; Shahidi, G.; Davari, B.; Chen, T.-C.; Goldblan, R.; Biery, G.; Moy, D.; Assaderaghi, F.; White, F.; Sleight, I.; Boiam, R.;
A partially-depleted SOI compact model - formulation and parameter extraction
2000 / IEEE / 0-7803-6305-1
By: Zamdmer, N.; Sherony, M.; Wagner, L.; Fung, S.K.H.; Assaderaghi, F.; Sleight, J.; Chen, T.C.; Lo, S.H.; Leobandung, E.; Michel, M.;
Reliability issues for silicon-on-insulator
2000 / IEEE / 0-7803-6438-4
By: Shahidi, G.; Bolam, R.; Badami, D.; Voldman, S.; Leobandung, E.; Wu, E.; Hook, T.; Mocuta, A.; Khare, M.; Assaderaghi, F.;
Design of a high performance PD SOI for the 0.18 /spl mu/m technology generation
2000 / IEEE / 964-360-057-2
By: Shahidi, G.G.; Chen, T.C.; Assaderaghi, F.; Rausch, W.; Sleight, J.W.; Sherony, M.J.; Leobandung, E.; Schulz, R.; Lo, S.-H.; Zamdmer, N.;
Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D
2002 / IEEE / 0-7803-7462-2
By: Lee, B.H.; Mocuta, A.; Welser, J.; Haensch, W.; Agnello, P.; Leobandung, E.; Yang, I.Y.; Ieong, M.; Ku, S.H.; Narasimha, S.; Jenkins, K.A.; Domenicucci, A.; Gribelyuk, M.; Kermel, H.; Sendelbach, M.; Jamin, F.; Mezzapelle, J.; Mitchell, R.M.; Chakravarti, A.; Mocuta, D.; Lavoie, C.; Cabral, C.; Chan, K.; Mo, R.; O'Neil, P.; Rim, K.; Sadana, D.; Bedell, S.; Chen, H.;
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
2004 / IEEE / 0-7803-8684-1
By: Cai, J.; Rim, K.; Leong, M.; Haensch, W.; Miller, R.; Leobandung, E.; Mocuta, A.; O'Neil, P.; Mocuta, D.; Ott, J.; Mitchell, R.; Uriarte, D.; Sadana, D.; Hovel, H.; Reznicek, A.; Bedell, S.; Wang, X.; Kumar, A.; Kanarsky, T.; Hergenrother, J.; Yin, H.; Lee, K.; Ren, Z.; Singh, D.; Bryant, A.; Jenkins, K.; Ouyang, C.;
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
2005 / IEEE / 4-900784-00-1
By: Leobandung, E.; Nayakama, H.; Mocuta, D.; Miyamoto, K.; Angyal, M.; Meer, H.V.; McStay, K.; Ahsan, I.; Allen, S.; Azuma, A.; Belyansky, M.; Bentum, R.-V.; Cheng, J.; Chidambarrao, D.; Dirahoui, B.; Fukasawa, M.; Gerhardt, M.; Gribelyuk, M.; Halle, S.; Harifuchi, H.; Harmon, D.; Heaps-Nelson, J.; Hichri, H.; Ida, K.; Inohara, M.; Inouc, I.C.; Jenkins, K.; Kawamura, T.; Kim, B.; Ku, S.-K.; Kumar, M.; Lane, S.; Liebmann, L.; Logan, R.; Melville, I.; Miyashita, K.; Mocuta, A.; O'Neil, P.; Ng, M.-F.; Nogami, T.; Nomura, A.; Norris, C.; Nowak, E.; Ono, M.; Panda, S.; Penny, C.; Radens, C.; Ramachandran, R.; Ray, A.; Rhee, S.-H.; Ryan, D.; Shinohara, T.; Sudo, G.; Sugaya, F.; Strane, J.; Tan, Y.; Tsou, L.; Wang, L.; Wirbeleit, F.; Wu, S.; Yamashita, T.; Yan, H.; Ye, Q.; Yoneyama, D.; Zamdmer, D.; Zhong, H.; Zhu, H.; Zhu, W.; Agnello, P.; Bukofsky, S.; Bronner, G.; Crabbe, E.; Freeman, G.; Huang, S.-F.; Ivers, T.; Kuroda, H.; McHerron, D.; Pellerin, J.; Toyoshima, Y.; Subbanna, S.; Kepler, N.; Su, L.;
RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology
2006 / IEEE / 1-4244-0005-8
By: Utomo, H.; Leobandung, E.; Mahorowala, A.; Mocuta, D.; Miyamoto, K.; Kumar, M.; Huang, S.; Gribelyuk, M.; Gabor, A.; Freeman, G.; Dirahoui, B.; Deshpande, S.; Azuma, A.; Chan, A.; Maciejewski, E.; Herman, J.; Berg, G.; Zimmerman, J.; Kimura, H.; Nowak, E.J.; Logan, R.; Glushchenkov, O.; Zamdmer, N.; Ahsan, I.; Walsh, B.;
Optimizing History Effects in 65nm PD-SOI CMOS
2006 / IEEE / 1-4244-0289-1
By: Mcstay, K.; Bhushan, M.; Robertson, D.; Ketchen, M.; Pelella, M.M.; Kawanaka, S.; Freeman, G.; Kawamura, T.; Liang, Q.; Huang, S.; Leobandung, E.; Miyamoto, K.;
On the Control of Short-Channel Effect for MOSFETs With Reverse Halo Implantation
2007 / IEEE
By: Qingqing Liang; Kawamura, T.; Huicai Zhong; Zhu, H.; Shih-Fen Huang; Leobandung, E.;
Implementation of Robust Nickel Alloy Salicide Process for High-Performance 65nm SOI CMOS Manufacturing
2007 / IEEE / 1-4244-0584-X
By: Strane, J.; Brown, D.; Jagannathan, J.; Pellerin, J.; Leobandung, E.; Deshpande, S.; Kahlert, V.; Streck, C.; Engelmann, H.J.; Knarr, R.; Murray, C.; Domenicucci, A.; DeHaven, P.; Frye, A.; Waidmann, S.; Huajie Chen; Peidous, I.; Kammler, T.; Gribelyuk, M.; Flaitz, P.; Besser, P.; Press, P.; Haran, B.; Suenaga, J.; Lavoie, C.;
Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner
2007 / IEEE / 978-4-900784-03-1
By: Leobandung, E.; Leach, D.; Chen, D.; Scholl, F.; Daewon Yang; Maxson, J.; Colt, J.; Kumar, M.; Huilong Zhu;
(110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/�m through channel stress and source drain external resistance (Rext) engineering
2007 / IEEE / 978-1-4244-1507-6
By: Yang, B.; Waite, A.; Agnello, P.; Luning, S.; Leobandung, E.; Khare, M.; Maciejewski, E.; Schepis, D.; Freeman, G.; Wachnik, R.; Sung, C.; Park, D.; Chen, X.; Utomo, H.; Luo, Z.; Narasimha, S.; Holt, J.; Liang, Q.; Liu, J.; Fisher, P.; Greene, B.; Nummy, K.; Pal, R.; Yin, H.; Yu, J.; Black, L.; Chidambarrao, D.; Domenicucci, A.; Wang, X.; Ku, S.H.; Wang, Y.; Meer, H.V.; Kim, B.; Nayfeh, H.; Kim, S.D.; Tabakman, K.;
A simple hardware-based statistical model on 65nm SOI CMOS technology
2007 / IEEE / 978-1-4244-1891-6
By: Wang, Y.; Cai, M.; Leobandung, E.; Walko, J.; Johnson, J.; Liang, Q.; Logan, R.; Springer, S.; Nowak, E.; Maciejewski, E.; Freeman, G.; Fried, D.;
SMT and enhanced SPT with recessed SD to improve CMOS device performance
2008 / IEEE / 978-1-4244-2185-5
By: Fang, S.; Tan, S.S.; Jagannathan, J.; Leobandung, E.; Divakaruni, R.; Yang, M.; Maciejewski, E.; Shang, H.; Li, Y.; Ng, H.; Greene, B.; Wang, Y.; Li, J.; Luo, Z.; Yan, J.; Belyansky, M.; Zuo, B.; Kim, J.J.; Liu, J.; Robinson, R.; Dyer, T.; Liang, Q.; Yuan, J.;
High performance and highly stable ultra-thin oxynitride for CMOS applications
2008 / IEEE / 978-1-4244-2185-5
By: Shepard, J.; Wenjuan Zhu; Leobandung, E.; Mocuta, D.; Schepis, D.; Ronsheim, P.; Ray, A.; Wei He;
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
2008 / IEEE / 978-1-4244-2377-4
By: Yang, B.; Takalkar, R.; Leobandung, E.; Pellerin, J.; Luning, S.; Maciejewski, E.; Schepis, D.; Mocuta, D.; Park, D.-G.; Sadana, D.; Grudowski, P.; Zollner, S.; Theodore, D.; Holt, J.; Meer, H.; Sun, S.; Aime, D.; Ren, Z.; Black, L.; Dube, A.; Weijtmans, J.W.; Li, J.; Johnson, J.B.; Faltermeier, J.; Madan, A.; Zhu, Z.; Turansky, A.; Xia, G.; Chakravarti, A.; Pal, R.; Chan, K.; Reznicek, A.; Adam, T.N.; Yang, B.; de Souza, J.P.; Harley, E.C.T.; Greene, B.; Gehring, A.; Cai, M.;
High performance 32nm SOI CMOS with high-k/metal gate and 0.149�m2 SRAM and ultra low-k back end with eleven levels of copper
2006 / IEEE / 978-1-4244-3308-7
By: Greene, B.; Liang, Q.; Amarnath, K.; Wang, Y.; Schaeffer, J.; Cai, M.; Liang, Y.; Saroop, S.; Cheng, J.; Rotondaro, A.; Han, S.-J.; Mo, R.; McStay, K.; Ku, S.; Pal, R.; Kumar, M.; Dirahoui, B.; Yang, B.; Tamweber, F.; Lee, W.-H.; Steigerwalt, M.; Weijtmans, H.; Holt, J.; Black, L.; Samavedam, S.; Turner, M.; Ramani, K.; Lee, D.; Belyansky, M.; Chowdhury, M.; Aime, D.; Min, B.; van Meer, H.; Yin, H.; Chan, K.; Angyal, M.; Zaleski, M.; Ogunsola, O.; Child, C.; Zhuang, L.; Yan, H.; Permanaa, D.; Sleight, J.; Guo, D.; Mittl, S.; Ioannou, D.; Wu, E.; Chudzik, M.; Park, D.-G.; Brown, D.; Luning, S.; Mocuta, D.; Maciejewski, E.; Henson, K.; Leobandung, E.;
On the systematic analysis of ring-delay performance using statistical behavior model
2009 / IEEE / 978-1-4244-6030-4
By: Liang, Y.; Cai, M.; Wang, Y.; Han, S.-J.; Greene, B.; Liang, Q.; Angello, P.; Leobandung, E.; Narasimha, S.; Maciejewski, E.; Henson, W.; Oldiges, P.; Nowak, E.; Johnson, J.; Amarnath, K.; Yang, F.;
Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond
2010 / IEEE / 978-1-4244-5450-1
By: Liu, Q.; Yagishita, A.; Sampson, R.; Doris, B.; Takayanagi, M.; Kleemeier, W.; Ishimaru, K.; Bu, H.; Hane, M.; Skotnicki, T.; Leobandung, E.; Berliner, N.; Levin, T.; Kuss, J.; Edge, L.F.; Johnson, R.; Upham, A.; Haran, B.; Reznicek, A.; Ponoth, S.; Sunamura, H.; Koburger, C.; Boeuf, F.; Monfray, S.; Kanakasabapathy, S.; Loubet, N.; Khakifirooz, A.; Kulkarni, P.; Yamamoto, T.; Cheng, K.; Fujiwara, M.; Cai, J.; Dorman, D.; Mehta, S.; Khare, P.; Yako, K.; Zhu, Y.; Mignot, S.;
A 0.063 �m2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
2010 / IEEE / 978-1-4244-5450-1
By: Basker, V.S.; Standaert, T.; Kawasaki, H.; Yeh, C.; Maitra, K.; Yamashita, T.; Faltermeier, J.; Adhikari, H.; Jagannathan, H.; Wang, J.; Sunamura, H.; Kanakasabapathy, S.; Schmitz, S.; Cummings, J.; Inada, A.; Lin, C.; Kulkarni, P.; Zhu, Y.; Kuss, J.; Yamamoto, T.; Kumar, A.; Wahl, J.; Yagishita, A.; Edge, L.F.; Kim, R.H.; Mclellan, E.; Holmes, S.J.; Johnson, R.C.; Levin, T.; Demarest, J.; Hane, M.; Takayanagi, M.; Colburn, M.; Paruchuri, V.K.; Miller, R.J.; Bu, H.; Doris, B.; McHerron, D.; Leobandung, E.; O'Neill, J.;

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