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Author: Lauer, I.

Results

A Comparison of Short-Channel Control in Planar Bulk and Fully Depleted Devices
2012 / IEEE
By: Dae-Gyu Park; Zhibin Ren; Young-Hee Kim; Kulkarni, P.; Chan, K.; Oldiges, P.; Jin Cai; Muralidhar, R.; Lauer, I.; Shahidi, G.;
A 0.021 �m2 trigate SRAM cell with aggressively scaled gate and contact pitch
2011 / IEEE / 978-1-4244-9949-6
By: Guillorn, M.A.; Chang, J.; Haensch, W.; Fuller, N.; Narayanan, V.; Sikorski, E.; Graham, W.; To, B.; Bucchignano, J.; Klaus, D.P.; Kratschmer, E.; Newbury, J.; Zhang, Z.; Lavoie, C.; Lauer, I.; Mauer, S.; Khater, M.; Bangsaruntip, S.; Brink, M.; Liu, F.; Majumdar, A.; Ott, J.A.; Bruce, R.; Pyzyna, A.; Engelmann, S.; Glodde, M.; Joseph, E.;
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)
2013 / IEEE
By: Cai, J.; Kim, D.; Lee, Y.; Sylvester, D.; Blaauw, D.; Koester, S. J.; Chang, L.; Lauer, I.;
Fully depleted n-MOSFETs on supercritical thickness strained SOI
2004 / IEEE
By: Lochtefeld, A.; Leitz, C.W.; Bulsara, M.T.; Somerville, M.; Antoniadis, D.A.; Badawi, H.; Currie, M.T.; Braithwaite, G.; Fiorenza, J.G.; Cheng, Z.-Y.; Langdo, T.A.; Lauer, I.;
Electron and hole mobility enhancements in sub-10 nm-thick strained silicon directly on insulator fabricated by a bond and etch-back technique
2004 / IEEE / 0-7803-8289-7
By: Hull, R.; Olubuyide, O.O.; Aberg, I.; Hoyt, J.L.; Chleirigh, C.N.; Li, J.; Antoniadis, D.A.; Lauer, I.;
Enhancement of electron mobility in ultrathin-body silicon-on-insulator MOSFETs with uniaxial strain
2005 / IEEE
By: Lauer, I.; Antoniadis, D.A.;
Transport and leakage in super-critical thickness strained silicon directly on insulator MOSFETs with strained Si thickness up to 135 nm
2005 / IEEE / 0-7803-9212-4
By: Cheng, Z.; Aberg, I.; Hoyt, J.L.; Antoniadis, D.A.; Lochtefeld, A.; Lauer, I.; Langdo, T.A.;
Challenges and Opportunities for High Performance 32 nm CMOS Technology
2006 / IEEE / 1-4244-0438-X
By: Narasimha, S.; Sheraw, C.; Guo, D.; Haran, B.; Fried, D.M.; Dokumaci, O.; Lauer, I.; Sleight, J.W.; Khare, M.; Haensch, W.; Sung, C.Y.; Sadana, D.; Oldiges, P.; Wang, X.; Steigerwalt, M.; Singh, D.;
Operational amplifier based test structure for transistor threshold voltage variation
2008 / IEEE / 978-1-4244-1800-8
By: Frank, D.J.; Stellari, F.; Lauer, I.; Pearson, D.J.; Ji, B.L.; Ketchen, M.B.; Chang, L.;
On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs
2008 / IEEE / 978-1-4244-1802-2
By: Sadana, D.; Park, D.-G.; Lauer, I.; Pal, R.; Kanarsky, T.; Chakravarti, A.; Harley, E.; Yang, B.; Weijtmans, J.W.; Black, L.; Dube, A.; Miller, J.; Adam, T.; Pinto, T.; Madan, A.; Zhu, Z.; Xia, G.; Chan, K.; Takalkar, R.; Yang, B.F.; Li, J.; Pei, G.; Zhibin Ren;
Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances
2008 / IEEE / 978-1-4244-1954-8
By: Fuller, N.; Ouyang, C.; Xinlin Wang; Huiming Bu; Joseph, E.; Huang, E.; Shahidi, G.; Purushothaman, S.; Chun-Yung Sung; Haensch, W.; Sunfei Fang; Lauer, I.; Mallikarjunan, A.; Tien Cheng; Shobha, H.; Simonyi, E.;
CMOS gate height scaling
2008 / IEEE / 978-1-4244-2185-5
By: Schonenberg, K.T.; Zhibin Ren; Butt, S.A.; Lauer, I.; Ontalus, V.;
Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation
2009 / IEEE
By: Lauer, I.; Pearson, D.J.; Ji, B.L.; Ketchen, M.B.; Chang, L.; Frank, D.J.; Stellari, F.;
Trigate 6T SRAM scaling to 0.06 �m2
2009 / IEEE / 978-1-4244-5641-3
By: Guillorna, M.; Chang, J.; Haensch, W.; Zhang, Y.; Fuller, N.; Narayanan, V.; Carter, S.; Sikorski, E.; Lauer, I.; Graham, W.; To, B.; Bucchignano, J.; Kratschmer, E.; Klaus, D.; Wang, C.; Newbury, J.; Gignac, L.; Frank, M.; Lavoie, C.; Ott, J.; Darnon, M.; Bryant, A.; Lin, C.-H.; Pyzyna, A.; Engelmann, S.; Joseph, E.; Fletcher, B.; Cabral, C.;
Effect of Uniaxial Strain on the Drain Current of a Heterojunction Tunneling Field-Effect Transistor
2011 / IEEE
By: Teherani, J.T.; Majumdar, A.; Lauer, I.; Solomon, P.M.; Koester, S.J.; Cai, J.; Luisier, M.;

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