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Author: Lage, C.

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The influence of titanium capped aluminum on N/sup +//P junction leakage
1988 / IEEE
By: Haas, F.; Whitwer, F.; Lage, C.;
An advanced self-aligned BiCMOS technology for high performance 1-megabit ECL I/O SRAMs
1989 / IEEE / 0-7803-0817-4
By: Haueisen, D.; DeLong, M.; Davies, T.; Lage, C.; Burger, W.R.; Small, J.; Whitwer, F.; Bastani, B.; Landau, B.; Huglin, G.;
Premetal planarization using spin-on-dielectric
1989 / IEEE
By: Davies, T.; Whitwer, F.; Lage, C.;
A submicron, double level metal process for high density memory applications
1990 / IEEE
By: Lage, C.; Davies, T.; Shenasa, M.; Sun, S.-P.; Garner, J.; Milligan, D.; Whitwer, F.;
Submicron BiCMOS technologies for supercomputer and high speed system implementation
1990 / IEEE / 0-8186-2079-X
By: Solheim, A.; Ilderem, V.; Bouknight, L.; Lage, C.; Iranmanesh, A.; Burger, W.; Bastani, B.; Small, J.; Biswal, M.; Lahri, R.;
An advanced 0.8 mu m complementary BiCMOS technology for ultra-high speed circuit performance
1990 / IEEE
By: Landau, B.; Lage, C.; Burger, W.R.; Small, J.; DeLong, M.;
Bipolar reliability optimization through surface compensation of the base profile
1992 / IEEE / 0-7803-0473-X
By: Burnett, J.D.; Hayden, J.D.; Lage, C.;
Tailoring interfacial oxide for polysilicon bit-cell contacts and emitters with in situ vapor HF interface cleaning and polysilicon deposition in a 4 Mbit BiCMOS fast static RAM
1992 / IEEE / 0-7803-0727-5
By: Lage, C.; Walczyk, F.; Blackwell, M.; Kaushik, V.;
Soft-error-rate improvement in advanced BiCMOS SRAMs
1993 / IEEE / 0-7803-0782-8
By: Bormann, A.; Lage, C.; Burnett, D.;
Thermally robust TiSi/sub 2/ on heavily doped polycrystalline silicon over severe topography
1992 / IEEE / 0-7803-0817-4
By: Perera, A.H.; Tatti, S.; Woo, M.P.; Sitaram, A.R.; Lage, C.;
A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM's
1994 / IEEE
By: Kirsch, H.; Hayden, J.D.; Lin, J.-H.; Pelley, P.; Sitaram, A.R.; Subrahmanyan, R.; Radhakrishna, S.; Kemp, K.; Roman, B.J.; Lage, C.; Woo, M.; Nguyen, B.-Y.; Gunderson, C.; Mazure, C.; Kenkare, P.; Taft, R.C.;
Soft error rate and stored charge requirements in advanced high-density SRAMs
1993 / IEEE / 0-7803-1450-6
By: Dreier, D.; Bormann, A.; Baker, K.; McNelly, T.; Burnett, D.; Lage, C.; Soorholtz, V.;
Device drive current degradation observed with retrograde channel profiles
1995 / IEEE / 0-7803-2700-4
By: Taylor, W.J.; Lage, C.; Lutze, J.W.; Venkatesan, S.;
Advanced SRAM technology-the race between 4T and 6T cells
1996 / IEEE / 0-7803-3393-4
By: Lage, C.; Subramanian, C.; Hayden, J.D.;
A trench isolation process for BiCMOS circuits
1993 / IEEE / 0-7803-1316-X
By: Poon, S.; Lage, C.;
A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization
1998 / IEEE / 0-7803-4770-6
By: Woo, M.; Bhat, M.; Craig, M.; Kenkare, P.; Wnag, X.; Tolic, F.; Chuang, H.; Parihar, S.; Schmidt, J.; Terpolilli, L.; Pena, R.; Derr, D.; Cave, N.; Crabtree, P.; Capetillo, M.; Filipiak, S.; Lii, T.; Nagy, A.; O'Meara, D.; Vuong, T.; Blackwell, M.; Larson, R.; Wilson, M.; Hayden, J.; Venkatesan, S.; Tsui, P.; Gilbert, P.; Perera, A.; Subramanian, C.; McNelly, T.; Misra, V.; Islam, R.; Smith, B.; Farkas, J.; Watts, D.; Denning, D.; Garcia, S.; Frisa, L.; Iyer, S.; Lage, C.;
A versatile 0.25 micron CMOS technology
1998 / IEEE / 0-7803-4774-9
By: Atwell, C.; Poon, S.; Yeargain, B.; Lage, C.; Kolar, D.; Hart, C.;
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver
2000 / IEEE
By: Ljung, P.B.; Lage, C.; Spasojevic, M.; Bachtold, M.;
A 180 nm copper/low-k CMOS technology with dual gate oxide optimized for low power and low cost consumer wireless applications
2000 / IEEE / 0-7803-6305-1
By: Lu, J.; Benavidas, J.; Sturtevant, J.; Huang, F.; Gilbert, P.; Das, A.; Sun, J.; Menke, D.; Green, K.; Hall, D.; Le, P.; Nangia, A.; Lii, T.; Pham, D.; Jallepalli, S.; Chen, J.; Nkansah, F.; Yeap, G.C.-F.; Lage, C.; Chung, J.; Banks, E.;
A highly versatile 0.18 /spl mu/m CMOS technology with dense embedded SRAM
2000 / IEEE / 0-7803-6305-1
By: Bhat, M.; Scott, J.; Grudowski, P.; Feng, C.; Lee, B.; Nagabushnam, R.; Moench, J.; Gunderson, C.; Schani, P.; Day, L.; Bishop, S.; Tian, H.; Chung, J.; Lage, C.; Ellis, J.; Herr, N.; Gilbert, P.; Das, A.; Nkansah, F.; Woo, M.; Wilson, M.; Derr, D.; Terpolilli, L.; Weidemann, K.; Stout, R.; Hamilton, A.; Lii, T.; Huang, F.; Cox, K.; Shi, S.;
A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications
2002 / IEEE / 0-7803-7312-X
By: Yeap, G.C.-F.; Chen, J.; Grudowski, P.; Jeon, Y.; Shiho, Y.; Qi, W.; Jallepalli, S.; Ramani, N.; Hellig, K.; Vishnubhotla, L.; Luo, T.; Tseng, H.; Du, Y.; Lim, S.; Abramowitz, P.; Reddy, C.; Parihar, S.; Singh, R.; Wright, M.; Patterson, K.; Benavides, N.; Bonser, D.; Gompel, T.V.; Conner, J.; Lee, J.J.; Rendon, M.; Hall, D.; Nghiem, A.; Stout, R.; Weidemann, K.; Duvallet, A.; Alvis, J.; Dyer, D.; Burnett, D.; Ingersoll, P.; Wimmer, K.; Veeraraghavan, S.; Foisy, M.; Hall, M.; Pellerin, J.; Wristers, D.; Woo, M.; Lage, C.;
3-D capacitance extraction of IC interconnects using field solvers and homogenization technique
2004 / IEEE
By: Ren, Z.; Lage, C.;
The SWAMI - A defect free and near-zero bird's-beak local oxidation process and its application in VLSI technology
1982 / IEEE
By: Fang, R.; Chiu, K.Y.; Tillman, R.; Angelos, S.; Lage, C.; Moll, J.L.; Lin, J.;
The sloped-wall SWAMI—A defect-free zero bird's-beak local oxidation process for scaled VLSI technology
1983 / IEEE
By: Chiu, K.Y.; Moll, J.L.; Cham, K.M.; Jung Lin; Lage, C.; Angelos, S.; Tillman, R.L.;
Poly emitter bipolar hot carrier effects in an advanced BiCMOS technology
1987 / IEEE
By: Lage, C.; Lahri, R.; Joshi, S.P.;
Advanced One Micron BICMOS Technology for High Speed 256K SRAMS
1987 / IEEE
By: Bastani, B.; Tuntasood, P.; Manoliu, J.; Bowman, T.; Bouknight, L.; Lahri, R.; Small, J.; Wong, L.; Lage, C.;
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
2008 / IEEE / 978-1-4244-1802-2
By: Chen, X.; Samavedam, S.; Narayanan, V.; Stein, K.; Hobbs, C.; Baiocco, C.; Li, W.; Jaeger, D.; Zaleski, M.; Yang, H.S.; Kim, N.; Lee, Y.; Zhang, D.; Kang, L.; Chen, J.; Zhuang, H.; Sheikh, A.; Wallner, J.; Aquilino, M.; Han, J.; Jin, Z.; Li, J.; Massey, G.; Kalpat, S.; Jha, R.; Moumen, N.; Mo, R.; Kirshnan, S.; Wang, X.; Chudzik, M.; Chowdhury, M.; Nair, D.; Reddy, C.; Teh, Y.W.; Kothandaraman, C.; Coolbaugh, D.; Pandey, S.; Tekleab, D.; Thean, A.; Sherony, M.; Lage, C.; Sudijono, J.; Lindsay, R.; Ku, J.H.; Khare, M.; Steegen, A.;
Scaling of 32nm low power SRAM with high-K metal gate
2008 / IEEE / 978-1-4244-2377-4
By: Yang, H.S.; Wong, R.; Stiffler, S.; Steegen, A.L.; Sudijono, J.; Pape, J.; Lage, C.; Khare, M.; Sherony, M.; Baiocco, C.V.; Jaeger, D.; Samavedam, S.; Stein, K.; Takasu, Y.; Wallner, J.; Teh, Y.W.; Sun, D.P.; Schiller, C.; Zhuang, L.; Arnaud, F.; Thean, A.; Hasumi, R.; Gao, Y.; Kim, N.S.; Lee, D.H.; Badrudduza, S.; Nair, D.; Ostermayr, M.; Kang, H.; Zhuang, H.; Li, J.; Kang, L.; Chen, X.;

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