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Author: Horiuchi, T.

Results

In situ multi-excitation chlorophyll fluorometer for phytoplankton measurements: Technologies and applications beyond conventional fluorometers

2011 / IEEE / 978-0-933957-39-8
By: Yoshida, M.; Nagasawa, Y.; Horiuchi, T.;

Quantum effects of ultrathin OTFT and fabrication processes by atomic hydrogen annealing

2012 / IEEE / 978-1-4673-0836-6
By: Heya, A.; Horiuchi, T.; Matsuo, N.;

Illumination-invariant representation for natural color images and its application

2012 / IEEE / 978-1-4673-1830-3
By: Horiuchi, T.; Ibrahim, A.; Tominaga, S.;

Neuromorphic VLSI second-order synapse

2015 / IEEE
By: Horiuchi, T.; Aggarwal, A.;

The impact of genistein on osteoporosis.

2010 / CABI
By: Horiuchi, T.;

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

1989 / IEEE
By: Enomoto, T.; Nakamura, K.; Horiuchi, T.; Yamada, H.; Yamashina, M.; Ando, K.; Okamoto, F.; Goto, J.;

200 MHz 16-bit BiCMOS signal processor

1989 / IEEE
By: Okamoto, F.; Goto, J.; Yamashina, M.; Enomoto, T.; Nakamura, K.; Horiuchi, T.; Yamada, H.;

GTO thyristor applications for HVDC transmission systems

1990 / IEEE
By: Tanaka, C.; Kashiwazaki, H.; Sampei, M.; Yamada, H.; Horiuchi, T.; Takahashi, T.;

Studies on aseismic measure for multistage thyristor valves

1991 / IEEE
By: Magoroku, H.; Horiuchi, T.; Takeda, H.; Ikegame, H.; Kobayashi, A.; Sampei, M.; Koyama, M.; Uchida, T.; Nakagaki, S.; Ohkubo, H.;

Development of VBO-free large capacity light-triggered thyristor valve

1992 / IEEE
By: Muraoka, Y.; Horiuchi, T.; Horiuchi, S.;

Computer aided surgery system (CAS): Development of surgical simulation and planning system with three dimensional graphic reconstruction

1990 / IEEE / 0-8186-2039-0
By: Dohi, T.; Tsuzuki, M.; Hashimoto, D.; Horiuchi, T.; Chinzei, K.; Suzuki, M.; Ohta, Y.;

Thin oxide charging current during plasma etching of aluminum

1991 / IEEE
By: Hu, C.; Horiuchi, T.; King, C.-C.; Shin, H.;

The effects of joint flexibility on robot motion control based on joint torque positive feedback

1991 / IEEE / 0-8186-2163-X
By: Horiuchi, T.; Hashimoto, M.; Hirabayashi, H.; Kiyosawa, Y.;

Clinical application of an active electrode using an operational amplifier

1992 / IEEE
By: Tomita, Y.; Nishimura, S.; Horiuchi, T.;

Approaching 20% efficiency with a-Si/poly-Si tandem solar cell

1991 / IEEE / 0-87942-636-5
By: Yoshimi, M.; Horiuchi, T.; Ma, W.; Hamakawa, Y.; Okamoto, H.; Hattori, K.;

A new BiCMOS gate array cell with diode connected bipolar driver

1990 / IEEE
By: Okumura, K.; Kudoh, O.; Yamazaki, K.; Sakai, I.; Horiuchi, T.;

Anomalous photovoltaic effect in ferroelectric polymers

1990 / IEEE / 0-7803-0190-0
By: Matsushige, K.; Horiuchi, T.; Kato, N.;

Formation of organic ferroelectric thin films by vacuum evaporation under electric field

1990 / IEEE / 0-7803-0190-0
By: Horiuchi, T.; Matsushige, K.; Yoshida, Y.;

A high performance asymmetric LDD MOSFET using selective oxide deposition technique

1992 / IEEE / 0-7803-0698-8
By: Horiuchi, T.; Okumura, K.; Murao, Y.; Homma, T.;

Computing motion using analog VLSI vision chips: an experimental comparison among four approaches

1991 / IEEE / 0-8186-2153-2
By: Bishofberger, B.; Horiuchi, T.; Bair, W.; Moore, A.; Koch, C.; Lazzaro, J.;

A 7-mask CMOS process with selective oxide deposition

1993 / IEEE
By: Murao, Y.; Homma, T.; Kanba, K.; Horiuchi, T.; Okumura, K.;

A 7 mask CMOS-technology utilizing liquid phase selective oxide deposition

1991 / IEEE / 0-7803-0243-5
By: Kanba, K.; Okumura, K.; Murao, Y.; Homma, T.; Horiuchi, T.;

Bipolar circuit reliability simulation

1990 / IEEE
By: Burnett, D.; Ku, C.; Horiuchi, T.;

Compressing data volume of left ventricular cineangiograms

1993 / IEEE
By: Horiuchi, T.; Toraichi, K.; Nagasaki, H.; Ohtaki, Y.; Kalman, R.E.;

Characterization of thin oxide damage during aluminum etching and photoresist ashing processes

1991 / IEEE / 0-7803-0036-X
By: Hu, C.; Horiuchi, T.; Moazzami, R.; King, C.-C.; Shin, H.;

An asymmetric sidewall process for high performance LDD MOSFET's

1994 / IEEE
By: Horiuchi, T.; Okumura, K.; Murao, Y.; Homma, T.;

A 300-MHz 16-b 0.5-/spl mu/m BiCMOS digital signal processor core LSI

1994 / IEEE
By: Suzuki, K.; Inoue, T.; Goto, J.; Yamashina, M.; Nomura, M.; Yamada, H.; Motomura, M.; Kumagai, K.; Enomoto, T.; Hamatake, N.; Horiuchi, T.; Shih, B.S.; Koseki, Y.;

A 300 MHz 16 b BiCMOS video signal processor

1993 / IEEE / 0-7803-0987-1
By: Goto, J.; Yamashina, M.; Takada, M.; Yamada, H.; Enomoto, T.; Kumagai, K.; Hamatake, N.; Horiuchi, T.; Inoue, T.; Shih, B.S.; Motomura, M.; Atsumo, T.; Kimura, T.; Koseki, Y.; Nomura, M.; Suzuki, K.;

A new titanium salicide process (DIET) for sub-quarter micron CMOS

1994 / IEEE / 0-7803-1921-4
By: Wakabayashi, H.; Horiuchi, T.; Okumura, K.; Kunio, T.; Mogami, T.; Nakamura, H.; Iskigami, T.;

An optimum design of a a-Sipoly-Si tandem solar cell

1993 / IEEE / 0-7803-1220-1
By: Hamakawa, Y.; Okamoto, I.I.; Goda, K.; Lim, C.C.; Horiuchi, T.; Ma, W.;

Resolution enhancement by oblique illumination optical lithography using a pupil filter

1993 / IEEE / 0-7803-1450-6
By: Takeuchi, Y.; Horiuchi, T.; Harada, K.; Matsuo, S.;

Automatic seal identification using fluency function approximation and relaxation matching method

1993 / IEEE / 0-8186-4960-7
By: Yang, Y.; Toraichi, K.; Horiuchi, T.;

Stamped character recognition method using range image

1993 / IEEE / 0-8186-4960-7
By: Yamada, H.; Toraichi, K.; Horiuchi, T.; Yamamoto, K.;

On method of training dictionaries for handwritten character recognition using relaxation matching

1993 / IEEE / 0-8186-4960-7
By: Yamamoto, K.; Toraichi, K.; Horiuchi, T.; Yamada, H.;

Generalized interpretation of optimization methods for labeling problems

1993 / IEEE / 0-8186-4960-7
By: Yamada, H.; Toraichi, K.; Horiuchi, T.; Iwana, T.; Yamamoto, K.;

On a method of noise reduction for 3D stamped character recognition using fluency-wavelet

1993 / IEEE / 0-7803-0971-5
By: Horiuchi, T.; Toraichi, K.; Haruki, R.; Yamamoto, K.; Yamada, H.;

Restoring to a polyhedron from three orthographic views by relaxation matching method

1993 / IEEE / 0-7803-0971-5
By: Yamamoto, K.; Ohiaki, Y.; Toraichi, K.; Horiuchi, T.; Yamada, H.;

Data compression method of left ventricular cineangiograms for their digital database system

1993 / IEEE / 0-7803-0971-5
By: Nagasaki, F.; Horiuchi, T.; Toraichi, K.; Ohtaki, Y.;

Extended relaxation method, including dynamic programming

1993 / IEEE / 0-7803-0971-5
By: Yamamoto, K.; Toraichi, K.; Horiuchi, T.; Yamada, H.;

Reduced oxide reliability due to multilevel metalization process

1995 / IEEE / 0-7803-2705-5
By: Noguchi, K.; Horiuchi, T.;

Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI

1996 / IEEE
By: Horiuchi, T.; Mizuno, M.; Iima, T.; Yamashina, M.;

A self-aligned counter-doped well process utilizing channeling ion implantation

1996 / IEEE
By: Horiuchi, T.; Nakamura, H.;

Novel salicide technology using Ti hydrogenation for 0.1 /spl mu/m CMOS

1996 / IEEE / 0-7803-3342-X
By: Ando, K.; Nishimoto, S.; Horiuchi, T.; Ishigami, T.; Matsubara, Y.;

100 MHz, 0.55 mm/sup 2/, 2 mW, 16-b stacked-CMOS multiplier-accumulator

1995 / IEEE / 0-7803-2584-2
By: Igura, H.; Yamashina, M.; Horiuchi, T.; Mogami, T.; Nakajima, K.; Wakabayashi, H.; Ito, H.; Furuta, K.; Izumikawa, M.;

A parallel relaxation architecture for handwritten character recognition

1995 / IEEE / 0-7803-2553-2
By: Horiuchi, T.; Mori, K.; Toraichi, K.; Wada, K.;

Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI

1995 / IEEE / 0-7800-2599-0
By: Iima, T.; Yamashina, M.; Horiuchi, T.; Mizuno, M.;

A symmetric 0.25 /spl mu/m CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography

1995 / IEEE / 0-7803-2602-4
By: Boulin, D.M.; Mansfield, W.M.; O'Connor, K.J.; Bevk, J.; Brasen, D.; Cheng, M.; Cirelli, R.A.; Eshraghi, S.A.; Green, M.L.; Guinn, K.V.; Hillenius, S.J.; Ibbotson, D.E.; Jacobson, D.C.; Kim, Y.O.; King, C.A.; Kistler, R.C.; Klemens, F.P.; Krisch, K.S.; Kornblit, A.; Lee, J.T.C.; Manchanda, L.; McNevin, S.C.; Moccio, S.V.; Monroe, D.P.; Ng, K.K.; O'Malley, M.L.; Rafferty, C.S.; Schwartz, G.P.; Vaidya, S.; Weber, G.R.; Feldman, L.C.; Pinto, M.R.; Itani, T.; Tounai, T.; Kasama, K.; Miyamoto, H.; Ikawa, E.; Hasagawa, E.; Ishitani, A.; Ito, H.; Horiuchi, T.; Saito, S.; Nakamae, M.;

A self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 /spl mu/m CMOS process

1995 / IEEE / 0-7803-2602-4
By: Horiuchi, T.; Nakamura, H.;

A 0.9 V 100 MHz 4 mW 2 mm/sup 2/ 16 b DSP core

1995 / IEEE / 0-7803-2495-1
By: Yamashina, M.; Horiuchi, T.; Mogami, T.; Nakajima, K.; Izumikawa, M.; Ito, H.; Furuta, K.; Igura, H.; Wakabayashi, H.;

In-circuit hot-carrier model and its application to inverter chain optimization

1996 / IEEE
By: Horiuchi, T.;

A new method to determine effective channel length, series resistance and threshold voltage

1996 / IEEE / 0-7803-2783-7
By: Horiuchi, T.; Ito, H.; Sasaki, M.;

Q-PSP learning: an exploitation-oriented Q-learning algorithm and its applications

1996 / IEEE / 0-7803-2902-3
By: Fujino, A.; Horiuchi, T.; Sawaragi, T.; Katai, O.;

Robust relaxation method for structural matching under uncertainty

1996 / IEEE / 0-8186-7282-X
By: Yamamoto, K.; Horiuchi, T.; Yamada, H.;

Automatic seal verification using three-dimensional reference seals

1996 / IEEE / 0-8186-7282-X
By: Horiuchi, T.; Haruki, R.; Yamamoto, K.; Yamada, H.;

Fuzzy interpolation-based Q-learning with continuous states and actions

1996 / IEEE / 0-7803-3645-3
By: Fujino, A.; Horiuchi, T.; Sawaragi, T.; Katai, O.;

A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core

1997 / IEEE
By: Horiuchi, T.; Mogami, T.; Nakajima, K.; Wakabayashi, H.; Yamashina, M.; Ito, H.; Furuta, K.; Igura, H.; Izumikawa, M.;

Low-k fluorinated amorphous carbon interlayer technology for quarter micron devices

1996 / IEEE / 0-7803-3393-4
By: Tatsumi, T.; Endo, K.; Matsubara, Y.; Horiuchi, T.; Sugai, K.; Ueno, H.;

Instantaneous space voltage vector controlled three-phase ZVS-PWM active converter with new auxiliary transformer assisted resonant DC link

1996 / IEEE / 0-7803-3507-4
By: Yonemori, H.; Kambe, A.; Nakaoka, M.; Horiuchi, T.;

Genetic algorithm involving coevolution mechanism to search for effective genetic information

1997 / IEEE / 0-7803-3949-5
By: Handa, H.; Horiuchi, T.; Sawaragi, T.; Katai, O.; Baba, N.;

Advanced Motion Control Implementation For Industrial Robots

1992 / IEEE / 0-7803-0737-2
By: Horiuchi, T.; Hashimoto, M.;

Correlation Between Electron Temperature Uniformity And Charging Damage In High Density Plasma Etching Tool

1997 / IEEE / 0-9651-5771-7
By: Tokashiki, K.; Horiuchi, T.; Miyamoto, H.; Noguchi, K.;

Relaxation optimizing processes in extended probabilistic space

1995 / IEEE / 0-8186-7128-9
By: Yamamoto, K.; Toraichi, K.; Horiuchi, T.; Yamada, H.;

Observation method for mathematical graphology

1995 / IEEE / 0-8186-7128-9
By: Horiuchi, T.; Toraichi, K.; Haruki, R.;

Fabrication and evaluation of niobium doped lead titanate thin films

1996 / IEEE / 0-7803-3355-1
By: Nishida, T.; Sakai, T.; Ibrahim, R.C.; Matsushige, K.; Shiosaki, T.; Horiuchi, T.;

Fuzzy interpolation-based Q-learning with profit sharing plan scheme

1997 / IEEE / 0-7803-3796-4
By: Fujino, A.; Horiuchi, T.; Sawaragi, T.; Katai, O.;

Scalable image coding by spline approximation for a gray-scale image

1997 / IEEE / 0-8186-7898-4
By: Horiuchi, T.; Haruki, R.;

Two-dimensional extension of nonlinear normalization method using line density for character recognition

1997 / IEEE / 0-8186-7898-4
By: Yamada, H.; Haruki, R.; Horiuchi, T.; Yamamoto, K.;

Pattern classification method by integrating interval feature values

1997 / IEEE / 0-8186-7898-4
By: Horiuchi, T.;

A 5-mask CMOS Technology

1997 / IEEE / 4-930813-75-1
By: Onishi, H.; Imai, K.; Nakamura, H.; Matsubara, Y.; Yamada, Y.; Horiuchi, T.; Tamura, T.; Sakai, T.;

Utility-interactive instantaneous sinewave space vector modulated bidirectional three phase power conditioner using resonant DC link

1997 / IEEE / 0-7803-4067-1
By: Nakaoka, M.; Nishida, Y.; Kurokawa, M.; Shimizu, T.; Horiuchi, T.; Sugawara, Y.;

High performance dual-gate FD-SOI CMOS process with an ultra thin TiSi/sub 2/

1997 / IEEE / 0-7803-3938-X
By: Furosawa, S.; Onishi, H.; Imai, K.; Nakamura, I.; Horiuchi, T.; Kumagai, K.; Ishigami, T.; Matsubara, Y.; Iwaki, K.; Yamada, T.;

Reliability of thin gate oxide under plasma charging caused by antenna topography-dependent electron shading effect

1997 / IEEE / 0-7803-4100-7
By: Noguchi, K.; Miyamoto, H.; Horiuchi, T.; Tokashiki, K.;

Gate electrode microstructure having stacked large-grain poly-Si with ultra-thin SiO/sub x/ interlayer for reliability in sub-micrometer CMOS

1997 / IEEE / 0-7803-4100-7
By: Watanuki, S.; Sasaki, M.; Ito, H.; Horiuchi, T.; Ueda, T.; Kimizuka, N.; Tsuboi, A.; Goto, Y.; Ito, T.; Uwasawa, K.;

Decision rule for pattern classification by integrating interval feature values

1998 / IEEE
By: Horiuchi, T.;

A 0.18 /spl mu/m fully depleted CMOS on 30 nm thick SOI for sub-1.0 V operation

1998 / IEEE / 0-7803-4770-6
By: Onishi, H.; Imai, K.; Horiuchi, T.; Ono, A.; Matsubara, Y.; Inoue, K.; Yamaguchi, K.;

Limitation of post-metallization annealing due to hydrogen blocking effect of multilevel interconnect

1998 / IEEE / 0-7803-4770-6
By: Clemens, J.T.; Horiuchi, T.; Noguchi, K.; Ito, S.;

Long-term reliability evaluation of power semiconductor devices used in substation rectifiers

1998 / IEEE / 0-7803-4752-8
By: Horiuchi, T.; Sugawara, Y.;

Effect of Low-Temperature Anneal during Multilevel Metallization Process on Plasma-Induced Oxide Damage

1996 / IEEE / 0-9651577-0-9
By: Horiuchi, T.; Noguchi, K.;

Suppression of topography-dependent charging damage to MOS devices using pulse-time-modulated plasma

1998 / IEEE / 0-9651577-2-5
By: Horiuchi, T.; Samukawa, S.; Ohtake, H.; Noguchi, K.;

Effect of electron temperature and electron density on topography dependent charging (TDC) damage in inductively coupled plasma etching tool

1998 / IEEE / 0-9651577-2-5
By: Nagase, M.; Araki, M.; Tokashiki, K.; Horiuchi, T.; Miyamoto, H.; Noguchi, K.;

RC delay reduction of 0.18 /spl mu/m CMOS technology using low dielectric constant fluorinated amorphous carbon

1998 / IEEE / 0-7803-4774-9
By: Horiuchi, T.; Gomi, H.; Tatsumi, T.; Iguchi, M.; Endo, K.; Kishimoto, K.; Tzou, E.; Matsubara, Y.; Moghadam, F.; Tribula, D.; Cheng, L.Y.; Xi, M.;

Conjunction search using a 1-D, analog VLSI-based, attentional search/tracking chip

1999 / IEEE / 0-7695-0056-0
By: Niebur, E.; Horiuchi, T.;

Adaptation of current signals with floating-gate circuits

1999 / IEEE / 0-7695-0043-9
By: Horiuchi, T.; Pesavento, A.; Koch, C.; Diorio, C.;

A Novel Low Resistance Salicide Technology (SWAN) For Quarter-micron CMOS

1993 / IEEE
By: Matsubara, Y.; Sekine, M.; Nishio, N.; Shinmura, T.; Noguchi, K.; Kitano, T.; Horiuchi, T.; Yamada, Y.;

Feasible performance evaluations of active resonant snubber-assisted three phase soft switching inverter

1999 / IEEE / 0-7803-5421-4
By: Ishibashi, M.; Hiraki, E.; Sugawara, Y.; Horiuchi, T.; Nakaoka, M.;

Fuzzy logic-based system coordination by redundant symbolization and reduction of environmental complexities

1999 / IEEE / 0-7803-5406-0
By: Sato, K.; Kawakami, H.; Hiraoka, T.; Horiuchi, T.; Katai, O.;

A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET

1999 / IEEE / 4-930813-93-X
By: Horiuchi, T.; Onishi, H.; Kimizuka, N.; Yamaguchi, K.; Shishiguchi, S.; Imai, K.;

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

1999 / IEEE / 4-930813-93-X
By: Imai, K.; Yamaguchi, K.; Mogami, T.; Yamamoto, T.; Kimizuka, N.; Horiuchi, T.;

Task-model based human robot cooperation using vision

1999 / IEEE / 0-7803-5184-3
By: Horiuchi, T.; Kimura, H.; Ikeuchi, K.;

Utility-interactive three-phase soft-switching pulse width modulated converter with active resonant snubbers in bridge leg sides for energy storage devices

1999 / IEEE / 0-7803-5735-3
By: Hiraki, E.; Yamamoto, H.; Nakaoka, M.; Sugawara, Y.; Horiuchi, T.; Nishida, K.; Konishi, Y.;

A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

1999 / IEEE / 0-7803-5410-9
By: Kuwata, T.; Horiuchi, T.; Kazama, K.; Ikeda, M.; Fujii, H.; Goto, Y.; Maruyama, S.; Noda, K.; Ono, A.; Kudo, T.; Onishi, H.; Kimizuka, N.; Yamaguchi, K.; Imai, K.;

Decision making process via constraint-oriented fuzzy logic based on Chu space theory

2000 / IEEE / 0-7803-5877-5
By: Hiraoka, T.; Horiuchi, T.; Sato, K.; Katai, O.; Kawakami, H.;

A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro

2000 / IEEE / 0-7803-5853-8
By: Takeda, K.; Takahashi, H.; Shimogawa, K.; Nakagawa, A.; Horiuchi, T.; Masuoka, S.; Nakamura, N.; Itoh, S.; Matsui, K.; Noda, K.; Iwasaki, T.; Toyoshima, H.; Aimoto, Y.;

On-chip multi-GHz clocking with transmission lines

2000 / IEEE / 0-7803-5853-8
By: Horiuchi, T.; Mogami, T.; Wakabayashi, H.; Surni, Y.; Anjo, K.; Mizuno, M.; Yamashina, M.;

A 1 GIPS 1 W single-chip tightly-coupled four-way multiprocessor with architecture support for multiple control flow execution

2000 / IEEE / 0-7803-5853-8
By: Nishi, N.; Inoue, T.; Fukuma, M.; Yamashina, M.; Motomura, M.; Horiuchi, T.; Ono, A.; Kazama, K.; Ikeda, M.; Kobinata, H.; Onoda, N.; Yamada, Y.; Hirota, Y.; Nakazawa, Y.; Yamazaki, T.; Manabe, T.; Inoue, H.; Matsuo, O.; Minami, K.; Mizuno, M.; Edahiro, M.; Ito, Y.; Shimada, S.; Nakamura, Y.; Ohsawa, T.; Sakai, J.; Shibayama, A.; Torii, S.; Matsushita, S.; Nomura, M.;

Nb-doped PbTiO/sub 3/ films deposited on MgO substrates

1999 / IEEE / 0-7803-5722-1
By: Shiosaki, T.; Ibrahim, R.C.; Matsushige, K.; Horiuchi, T.;

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield

2000 / IEEE / 0-7803-5809-0
By: Nakamura, N.; Aimoto, Y.; Takeda, K.; Ikezawa, N.; Kawamoto, H.; Masuoka, S.; Toyoshima, H.; Matsui, K.; Noda, K.; Horiuchi, T.; Ito, S.; Iwasaki, T.;

A 70 nm gate length CMOS technology with 1.0 V operation

2000 / IEEE / 0-7803-6305-1
By: Ono, A.; Horiuchi, T.; Imai, K.; Ikezawa, N.; Fukai, T.; Matsuda, T.; Fukasaku, K.;

NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation

2000 / IEEE / 0-7803-6305-1
By: Liu, C.T.; Iizuka, T.; Imai, K.; Yamaguchi, K.; Kimizuka, N.; Horiuchi, T.; Keller, R.C.;

A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip

2000 / IEEE / 0-7803-6305-1
By: Hamanaka, N.; Toda, T.; Ohashi, T.; Kimizuka, N.; Horiuchi, T.; Hasegawa, E.; Imai, K.; Goto, Y.;

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