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Author: Grider, T.

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Effect of F on B penetration through gate oxide for BF/sub 2/ implants used to obtain ultra-shallow junctions by RTA

1996 / IEEE / 0-7803-3289-X
By: McNeil, V.; Grider, T.; List, S.; Banejee, S.; Craig, M.; Sultan, A.;

Effects of advanced processes on hot carrier reliability

1998 / IEEE / 0-7803-4400-6
By: McNeil, V.; Grider, T.; Aur, S.; Eklund, R.; Holloway, T.;

Short channel effects and delay hysteresis for 0.25 /spl mu/m SOI technology with minimal process changes from the bulk technology

1998 / IEEE / 0-7803-4500-2
By: Joyner, K.; Thakar, G.V.; Grider, T.; Unnikrishnan, S.; Jacobs, J.B.; Houston, T.W.; Eklund, R.H.;

Advanced CMOS transistors with a novel HfSiON gate dielectric

2002 / IEEE / 0-7803-7312-X
By: Bevan, M.J.; Grider, T.; Douglas, M.; Tsung, L.; Laaksonen, R.T.; Bu, H.; Khamankar, R.; Shanware, A.; Chambers, J.J.; Visokay, M.R.; Rotondaro, A.L.P.; Colombo, L.; Kuan, R.; McPherson, J.;

A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length

2002 / IEEE / 0-7803-7462-2
By: Mercer, D.; Grider, T.; Kuan, R.; Tsung, L.; Ruan, J.; Hewson, M.; Montgomery, C.; Lin, C.; Xu, Y.; Gurba, A.; Zhao, J.; Miles, D.; Lu, J.P.;

A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer

2003 / IEEE / 4-89114-033-X
By: AlShareef, H.; Varghese, A.; Miles, D.; Kirkpatrick, B.; Robertson, L.; Goodwin, M.; Niimi, H.; Khamankar, R.; Hornung, B.; Grider, T.; Machala, C.; Thakar, G.; Bowen, C.; Rathsack, B.; Deloach, J.; Lu, J.P.; Smith, B.; Blatchford, J.; Zhang, X.; Gurba, A.; Chakravarthi, S.; Chidambaram, P.R.; Nicollian, P.; Bevan, M.;

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

2004 / IEEE / 0-7803-8289-7
By: Khamankar, R.; Bu, H.; Grider, T.; Machala, C.; Aur, S.; Somervell, M.; Kaneshige, C.; Tran, J.; DeLoach, J.; Rathsack, B.; Ukraintsev, V.; Gurba, A.; Varghese, A.; Alshareef, H.; Hall, L.; Farber, D.; Hewson, M.; Miles, D.; Kirkpatrick, B.; Nicollian, P.; Lu, J.P.; Hornung, B.; Blatchford, J.; Smith, B.; Niimi, H.; Krishnan, A.; Bevan, M.; Bowen, C.; Chakravarthi, S.; Chidambaram, P.R.;

Nickel SALICIDE Process Technology for CMOS Devices of 90nm Node and Beyond

2006 / IEEE / 1-4244-0047-3
By: Lu, J.P.; Miles, D.S.; Montgomery, C.; Mercer, D.; Grider, T.; Johnson, F.S.; Griffin, A.F.Jr.; Lin, B.Y.; Xu, Y.Q.; Hall, L.H.; Liu, X.; Robertson, L.S.; Guldi, R.L.; Corum, D.; Ramappa, D.A.; Obeng, Y.; Mehrad, F.; Yu, S.F.; Crank, S.; Bonifield, T.; Chen, P.J.; Yue, D.F.; DeLoach, J.;

A designer friendly 45nm high performance technology with in-situ C-doped e-SiGe & dual stress liner in SRAM

2008 / IEEE / 978-1-4244-1802-2
By: Khamankar, R.; Grider, T.; Shinn, G.; O'Brien, C.; Machala, C.; Blatchford, J.; Yu, S.; Riley, D.; Prins, S.; Olubuyide, O.; Montgomery, C.; Lowry, T.; Liu, L.; Lin, C.; Krishnan, A.; Kirmse, K.; Kirkpatrick, B.; Kim, T.; Hornung, B.; Gu, Y.; Fujii, I.; Corum, D.; Bu, H.; Bowen, C.;

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