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Author: Gilmer, D.

Results

Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D world

2012 / IEEE / 978-1-4673-0145-9
By: Loh, W.; Arkalgud, S.; Hill, R.; Ang, K.; Kang, C.; Jammy, R.; Oh, J.; Hummler, K.; Kirsch, P.; Hobbs, C.; Bersuker, G.; Gilmer, D.; Lee, R.;

Evaluation of variability and RTN in scaled RRAM

2014 / IEEE
By: Veksler, Dmitry; Bersuker, G.; Butcher, B.; Gilmer, D.; Matthews, K.; Deora, S.;

Sub-quarter micron CMOS process for TiN-gate MOSFETs with TiO/sub 2/ gate dielectric formed by titanium oxidation

1999 / IEEE / 4-930813-93-X
By: Hegde, R.; Hobbs, C.; Tseng, H.; Gilmer, D.; Tobin, P.; Adetutu, O.; Huang, F.; Weddington, D.; Nagabushnam, R.; O'Meara, D.; Reid, K.; La, L.; Grove, L.; Rossow, M.; Maiti, B.;

Sub-quarter micron Si-gate CMOS with ZrO/sub 2/ gate dielectric

2001 / IEEE / 0-7803-6412-0
By: Gilmer, D.; Rai, R.; Reid, K.; Dip, L.; Hobbs, C.; Tobin, P.; Workman, D.; Locke, J.; Dumbuya, F.; Backer, S.; Conner, J.; Bagchi, S.; Hegde, R.; Prabhu, L.; Rendon, M.; Schippers, M.; Farber, D.; Huang, F.; Weddington, D.; Tseng, H.; Samavedam, S.; Cheng, B.; Taylor, B.; Ma, T.;

Fermi level pinning at the polySi/metal oxide interface

2003 / IEEE / 4-89114-033-X
By: Grant, J.; Dip, L.; Taylor, B.; Samavedam, S.; Dhandapani, V.; Fonseca, L.; Hobbs, C.; Tobin, P.; White, B.; Tseng, H.; Hebert, L.; Rai, R.; Lovejoy, L.; Roan, D.; Garcia, R.; Gilmer, D.; Hegde, R.; Triyoso, D.;

Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS

2006 / IEEE / 1-4244-0438-X
By: Taylor, W.J.; Capasso, C.; Venkatesan, S.; White, S.B.; Samavedam, S.B.; Tobin, P.J.; Cave, N.; Foisy, M.; Burnett, D.; Jovanovic, D.; Smith, J.; Hebert, L.; La, L.B.; Nguyen, J.-Y.; Roan, D.; Haggag, A.; Kalpat, S.; Triyoso, D.H.; Happ, C.; Raymond, M.; Martinez, A.; Luckowski, E.; Schaeffer, J.; Hegde, R.I.; Min, B.; Winstead, B.; Verret, E.; Loiko, K.; Gilmer, D.;

A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

2006 / IEEE / 978-1-4244-3308-7
By: Tateiwa, K.; Young, C.; Park, C.; Huang, J.; Hussain, M.M.; Park, C.S.; Jammy, R.; Tseng, H.-H.; Kirsch, P.D.; Bersuker, G.; Heh, D.; Lysaght, P.; Price, J.; Rader, K.; Gilmer, D.; Cruz, M.; Park, H.K.;

Charge loss in TANOS devices caused by Vt sensing measurements during retention

2010 / IEEE / 978-1-4244-6721-1
By: Kirsch, P.D.; Taylor, W.; Pavan, P.; Larcher, L.; Padovani, A.; Bersuker, G.; Hwang, H.; Jo, M.; Lim, K.Y.; Gilmer, D.; Park, H.;

Tunnel oxide degradation in TANOS devices and its origin

2010 / IEEE / 978-1-4244-5063-3
By: Chang, M.; Hwang, H.; Kang, C.Y.; Goel, N.; Young, C.; Gilmer, D.; Lim, K.Y.; Veksler, D.; Jo, M.; Bersuker, G.; Park, H.; Jammy, R.; Kirsch, P.D.; Tseng, H.;

Modeling of the Forming Operation in HfO2-Based Resistive Switching Memories

2011 / IEEE / 978-1-4577-0226-6
By: Vandelli, L.; Pavan, P.; Gilmer, D.; Bersuker, G.; Larcher, L.; Padovani, A.;

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