Your Search Results

Use materials by this author in your textbook!

AcademicPub holds over eight million pieces of educational content such as case studies and journal articles for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!

Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Author: Chidambarrao, D.

Results

Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model

1998 / IEEE / 0-7803-4774-9
By: Wong, H.-S.P.; Laux, S.E.; Solomon, P.M.; MeiKei Ieong; Chidambarrao, D.;

Effects of stress concentration on metal voiding during dielectric deposition

1999 / IEEE / 0-7803-5502-4
By: Flaitz, P.L.; Naeem, M.D.; Chidambarrao, D.;

Vertical pass transistor design for sub-100 nm DRAM technologies

2002 / IEEE / 0-7803-7312-X
By: Chidambarrao, D.; Mandelman, J.; Mueller, W.; Bronner, G.; Crabbe, E.; Bergner, W.; Divakaruni, R.; McStay, K.; Hummler, K.; Li, Y.; Wang, G.; Weybright, M.; Tews, H.; Beintner, J.;

Technologies for scaling vertical transistor DRAM cells to 70 nm

2003 / IEEE / 4-89114-033-X
By: Divakaruni, R.; Bronner, G.; Crabbe, E.; Jammy, R.; Li, Y.; Feng, G.; Edleman, N.; Dobuzinsky, D.; Strane, J.; Settlemyer, K.; Economikos, L.; Akatsu, H.; Weybright, M.; Chidambarrao, D.; Saroop, S.; Park, D.-G.; Chudzik, M.; Belyansky, M.; Radens, C.;

Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies

2003 / IEEE / 0-7803-7765-6
By: Weybright, M.; McStay, K.; Chidambarrao, D.; Crabbe, E.; Li, Y.; Beintner, J.; Mandelman, J.;

On the retention time distribution of dual-channel vertical DRAM technologies

2003 / IEEE / 0-7803-7765-6
By: Mueller, W.; Crabbe, E.; Bergner, W.; Divakaruni, R.; Hummler, K.; Wang, G.; Poechmueller, P.; McStay, K.; Chidambarrao, D.; Casarotto, D.; Li, Y.; Beintner, J.; Bronner, G.;

Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications

2004 / IEEE
By: Bronner, G.; Pochmuller, P.; Divakaruni, R.; Voigt, P.; Beintner, J.; Chidambarrao, D.; Knorr, A.; Li, Y.;

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

2004 / IEEE / 0-7803-8684-1
By: Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; van Bentum, R.; Grasshoff, G.; Schwan, C.; Ehrichs, E.; Goad, S.; Buller, J.; Krishnan, S.; Greenlaw, D.; Raab, M.; Kepler, N.; Yang, H.S.; Malik, R.; Narasimha, S.; Li, Y.; Divakaruni, R.; Agnello, P.; Allen, S.; Antreasyan, A.; Arnold, J.C.; Bandy, K.; Belyansky, M.; Bonnoit, A.; Bronner, G.; Chan, V.; Chen, X.; Chen, Z.; Chidambarrao, D.; Chou, A.; Clark, W.; Crowder, S.W.; Engel, B.; Harifuchi, H.; Huang, S.F.; Jagannathan, R.; Jamin, F.F.; Kohyama, Y.; Kuroda, H.; Lai, C.W.; Lee, H.K.; Lee, W.-H.; Lim, E.H.; Lai, W.; Mallikarjunan, A.; Matsumoto, K.; McKnight, A.; Nayak, J.; Ng, H.Y.; Panda, S.; Rengarajan, R.; Steigerwalt, M.; Subbanna, S.; Subramanian, K.; Sudijono, J.; Sudo, G.; Sun, S.-P.; Tessier, B.; Toyoshima, Y.; Tran, P.; Wise, R.; Wong, R.; Yang, I.Y.; Wann, C.H.; Su, L.T.; Horstmann, M.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Salz, H.;

Dual stress liner enhancement in hybrid orientation technology

2005 / IEEE / 4-900784-00-1
By: Sheraw, C.D.; Khare, M.; Fried, D.M.; Costrini, G.; Kanarsky, T.; Lee, W.-H.; Chan, V.; Fischetti, M.V.; Holt, J.; Black, L.; Naeem, M.; Panda, S.; Economikos, L.; Groschopf, J.; Kapur, A.; Li, Y.; Mo, R.T.; Bonnoit, A.; Degraw, D.; Luning, S.; Chidambarrao, D.; Wang, X.; Bryant, A.; Brown, D.; Sung, C.-Y.; Agnello, P.; Ieong, M.; Huang, S.-F.; Chen, X.; Yang, M.;

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

2005 / IEEE / 4-900784-00-1
By: Leobandung, E.; Nayakama, H.; Mocuta, D.; Miyamoto, K.; Angyal, M.; Meer, H.V.; McStay, K.; Ahsan, I.; Allen, S.; Azuma, A.; Belyansky, M.; Bentum, R.-V.; Cheng, J.; Chidambarrao, D.; Dirahoui, B.; Fukasawa, M.; Gerhardt, M.; Gribelyuk, M.; Halle, S.; Harifuchi, H.; Harmon, D.; Heaps-Nelson, J.; Hichri, H.; Ida, K.; Inohara, M.; Inouc, I.C.; Jenkins, K.; Kawamura, T.; Kim, B.; Ku, S.-K.; Kumar, M.; Lane, S.; Liebmann, L.; Logan, R.; Melville, I.; Miyashita, K.; Mocuta, A.; O'Neil, P.; Ng, M.-F.; Nogami, T.; Nomura, A.; Norris, C.; Nowak, E.; Ono, M.; Panda, S.; Penny, C.; Radens, C.; Ramachandran, R.; Ray, A.; Rhee, S.-H.; Ryan, D.; Shinohara, T.; Sudo, G.; Sugaya, F.; Strane, J.; Tan, Y.; Tsou, L.; Wang, L.; Wirbeleit, F.; Wu, S.; Yamashita, T.; Yan, H.; Ye, Q.; Yoneyama, D.; Zamdmer, D.; Zhong, H.; Zhu, H.; Zhu, W.; Agnello, P.; Bukofsky, S.; Bronner, G.; Crabbe, E.; Freeman, G.; Huang, S.-F.; Ivers, T.; Kuroda, H.; McHerron, D.; Pellerin, J.; Toyoshima, Y.; Subbanna, S.; Kepler, N.; Su, L.;

Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths

2005 / IEEE / 0-7803-9212-4
By: Chidambarrao, D.; Venigalla, R.; Dokumaci, O.; Black, L.; Nayfeh, H.; Ren, Z.; Sleight, J.W.; Hergenrother, J.M.; Singh, D.V.; Haensch, W.; Ieong, M.; Guarini, K.W.; Khare, M.; Ott, J.A.; Nomura, A.; Tessier, B.L.; Pan, J.;

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

2005 / IEEE / 0-7803-9268-X
By: Lee, W.-H.; Waite, A.; Nii, H.; Nayfeh, H.M.; McGahay, V.; Nakayama, H.; Fried, D.; Chen, H.; Black, L.; Bolam, R.; Cheng, J.; Chidambarrao, D.; Christiansen, C.; Cullinan-Scholl, M.; Davies, D.R.; Domenicucci, A.; Fisher, P.; Fitzsimmons, J.; Gill, J.; Gribelyuk, M.; Harmon, D.; Holt, J.; Ida, K.; Kiene, M.; Kluth, J.; Labelle, C.; Madan, A.; Malone, K.; McLaughlin, P.V.; Minami, M.; Mocuta, D.; Murphy, R.; Muzzy, C.; Newport, M.; Panda, S.; Peidous, I.; Sakamoto, A.; Sato, T.; Sudo, G.; VanMeer, H.; Yamashita, T.; Zhu, H.; Agnello, P.; Bronner, G.; Freeman, G.; Huang, S.-F.; Ivers, T.; Luning, S.; Miyamoto, K.; Nye, H.; Pellerin, J.; Rim, K.; Schepis, D.; Spooner, T.; Chen, X.; Khare, M.; Horstmann, M.; Wei, A.; Kammler, T.; Hontschel, J.; Bierstedt, H.; Engelmann, H.-J.; Hellmich, A.; Hempel, K.; Koerner, G.; Neu, A.; Otterbach, R.; Reichel, C.; Trentsch, M.; Press, P.; Frohberg, K.; Schaller, M.; Salz, H.; Hohage, J.; Ruelke, H.; Klais, J.; Raab, M.; Greenlaw, D.; Kepler, N.;

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

2005 / IEEE / 0-7803-9268-X
By: Horstmann, M.; Wei, A.; Kammler, T.; Hontschel, J.; Bierstedt, H.; Feudel, T.; Frohberg, K.; Gerhardt, M.; Hellmich, A.; Hempel, K.; Hohage, J.; Javorka, P.; Klais, J.; Koerner, G.; Lenski, M.; Neu, A.; Otterbach, R.; Press, P.; Reichel, C.; Trentsch, M.; Trui, B.; Salz, H.; Schaller, M.; Engelmann, H.-J.; Herzog, O.; Ruelke, H.; Hubler, P.; Stephan, R.; Greenlaw, D.; Raab, M.; Kepler, N.; Chen, H.; Chidambarrao, D.; Fried, D.; Holt, J.; Lee, W.; Nii, H.; Panda, S.; Sato, T.; Waite, A.; Liming, S.; Rim, K.; Schepis, D.; Khare, M.; Huang, S.F.; Pellerin, J.; Su, L.T.;

Design of high performance PFETs with strained si channel and laser anneal

2005 / IEEE / 0-7803-9268-X
By: Luo, Z.; Rim, K.; Ng, H.; Schepis, D.; Amos, R.; Mishra, S.; Lee, J.; Ajmera, A.; Lindsay, R.; Gluschenkov, O.; Turansky, A.; Madan, A.; Davis, R.; Li, J.; Chidambarrao, D.; Holt, J.; Sato, T.; Panda, S.; Greene, B.; Rovedo, N.; Kim, J.; Chong, Y.F.;

Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths

2005 / IEEE / 0-7803-9268-X
By: Hergenrother, J.M.; Natzle, W.; Sleight, J.W.; Singh, D.V.; Haensch, W.; Ieong, M.; Ott, J.A.; Nomura, A.; Tessier, B.L.; Ren, Z.; Pan, J.; Venigalla, R.; Chidambarrao, D.; Nakayama, H.; Chang, J.B.; Black, L.; Dokumaci, O.; Jenkins, K.A.;

Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs

2006 / IEEE
By: Sleight, J.W.; Ren, Z.; Singh, D.V.; Nayfeh, H.M.; Haensch, W.; Ieong, M.; Guarini, K.W.; Khare, M.; Ott, J.A.; Tessier, B.L.; Hergenrother, J.M.; Natzle, W.; Pan, J.; Venigalla, R.; Chidambarrao, D.; Black, L.; Dokumaci, O.;

Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

2006 / IEEE / 1-4244-0005-8
By: Chen, X.; Fang, S.; Davis, C.; Ku, J.H.; Schiml, T.; Sudijono, J.; Yang, I.; Steegen, A.; Coolbough, D.; Hierlemann, M.; Ng, H.; Amos, R.; Sherony, M.; Belyansky, M.; Widodo, J.; Tjoa, T.; Edleman, N.; Kwon, O.; Panda, S.; Yuan, J.; Nguyen, P.; Nivo, N.; Luo, Z.; Chidambarrao, D.; Stierstorfer, R.; Kim, J.; Gao, W.; Dyer, T.; Teh, Y.W.; Tan, S.S.; Ko, Y.; Baiocco, C.; Ajmera, A.; Park, J.;

300GHz Transistor Performance in Production CMOS Technologies

2006 / IEEE / 0-7803-9748-7
By: Pekarik, J.; Chidambarrao, D.; Jagannathan, B.;

Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure

2006 / IEEE / 1-4244-0438-X
By: Henson, W.K.; Yaocheng Liu; Donaton, R.A.; Chang, P.; Johnson, J.; Chidambarrao, D.; Holt, J.; Wann, C.; Rim, K.; Madan, A.; Domenicucci, A.; Jinghong Li; Xi Li;

Technology-Model-Product Parallel Design for High Performance and Rapid Time to Market 65nm Technology-Generation Microprocessors

2007 / IEEE / 1-4244-0652-8
By: Greene, B.J.; McStay, K.; Logan, L.R.; Freeman, G.; Crabbe, E.; Springer, S.; Slisher, D.; McCullen, J.; Williams, R.; Chidambarrao, D.; Zamdmer, N.; Dufrene, B.; Clougherty, F.; Friedrich, J.; Ku, S.-H.; Nowak, E.; Na, M.-H.; Liang, Q.;

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

2007 / IEEE / 978-4-900784-03-1
By: Yang, B.F.; Nummy, K.; Agnello, P.; Luning, S.; Khare, M.; Schepis, D.; Sung, C.Y.; Park, D.; Chen, X.; Holt, J.; Wehella-gamage, D.; Sheraw, C.; Kim, S.D.; Chidambarrao, D.; Johnson, J.; Meer, H.V.; Fisher, P.; Narasimha, S.; Kim, B.; Liu, Y.; Yin, H.; Gossmann, H.; Waite, A.; Black, L.;

(110) channel, SiON gate-dielectric PMOS with record high I_on=1 mA/�m through channel stress and source drain external resistance (R_ext) engineering

2007 / IEEE / 978-1-4244-1507-6
By: Yang, B.; Waite, A.; Agnello, P.; Luning, S.; Leobandung, E.; Khare, M.; Maciejewski, E.; Schepis, D.; Freeman, G.; Wachnik, R.; Sung, C.; Park, D.; Chen, X.; Utomo, H.; Luo, Z.; Narasimha, S.; Holt, J.; Liang, Q.; Liu, J.; Fisher, P.; Greene, B.; Nummy, K.; Pal, R.; Yin, H.; Yu, J.; Black, L.; Chidambarrao, D.; Domenicucci, A.; Wang, X.; Ku, S.H.; Wang, Y.; Meer, H.V.; Kim, B.; Nayfeh, H.; Kim, S.D.; Tabakman, K.;

Reduction of RTA-driven intra-die variation via model-based layout optimization

2006 / IEEE / 978-1-4244-3308-7
By: Clougherty, F.; Mocuta, A.; Nowak, E.; Landis, H.; Goplen, B.; Gluschenkov, O.; Scott, J.C.; Chen, X.; Crabbe, E.; Divakaruni, R.; Hefferon, G.; Shang, H.; Li, Y.; Deshpande, S.; Ferris, J.; Chang, P.; Yu, J.; Chidambarrao, D.; Eller, M.; Lai, C.W.; Zamdmer, N.; Hook, T.;

Return To Top