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Author: Cartier, E.

Results

Voltage Ramp Stress for Hot-Carrier Screening of Scaled CMOS Devices

2012 / IEEE
By: Kerber, A.; Cartier, E.; McMahon, W.;

High performance bulk planar 20nm CMOS technology for low power mobile applications

2012 / IEEE / 978-1-4673-0847-2
By: Huiling Shang; Jain, S.; Josse, E.; Alptekin, E.; Nam, M.H.; Kim, S.W.; Cho, K.H.; Kim, I.; Liu, Y.; Yang, X.; Wu, X.; Ciavatti, J.; Kim, N.S.; Vega, R.; Kang, L.; Meer, H.V.; Samavedam, S.; Celik, M.; Soss, S.; Utomo, H.; Ramachandran, R.; Lai, W.; Sardesai, V.; Tran, C.; Kim, J.Y.; Park, Y.H.; Tan, W.L.; Shimizu, T.; Joy, R.; Strane, J.; Tabakman, K.; Lalanne, F.; Montanini, P.; Babich, K.; Kim, J.B.; Economikos, L.; Cote, W.; Reddy, C.; Belyansky, M.; Arndt, R.; Kwon, U.; Wong, K.; Koli, D.; Levedakis, D.; Lee, J.W.; Muncy, J.; Krishnan, S.; Schepis, D.; Chen, X.; Kim, B.D.; Tian, C.; Linder, B.P.; Cartier, E.; Narayanan, V.; Northrop, G.; Menut, O.; Meiring, J.; Thomas, A.; Aminpur, M.; Park, S.H.; Lee, K.Y.; Kim, B.Y.; Rhee, S.H.; Hamieh, B.; Srivastava, R.; Koshy, R.; Goldberg, C.; Pallachalil, M.; Chae, M.; Ogino, A.; Watanabe, T.; Oh, M.; Mallela, H.; Codi, D.; Malinge, P.; Weybright, M.; Mann, R.; Mittal, A.; Eller, M.; Lian, S.; Li, Y.; Divakaruni, R.; Bukofsky, S.; Kim, J.D.; Sudijono, J.; Neumueller, W.; Matsuoka, F.; Sampson, R.;

Improving and optimizing reliability in future technologies with high-κ dielectrics

2013 / IEEE
By: Linder, Barry P.; Cartier, E.; Krishnan, S.; Wu, E.;

Electron transport in thin insulating films; physics and effects on dielectric aging

1988 / IEEE
By: Dersch, H.; Cartier, E.; Pfluger, P.;

Correlation between theory and data for mechanisms leading to dielectric breakdown

1994 / IEEE / 0-7803-1921-4
By: DiMaria, D.J.; Bolam, R.J.; Vollertsen, R.-P.; Abadeer, W.W.; Cartier, E.;

Determination of physical parameters and reliability of ultra thin oxides

1997 / IEEE / 0-7803-4205-4
By: Cartier, E.;

Breakdown measurements of ultra-thin SiO/sub 2/ at low voltage

2000 / IEEE / 0-7803-6305-1
By: Linder, B.P.; Wachnik, R.A.; Cartier, E.; Han, L.-K.; DiMaria, D.J.; Vayshenker, A.; McKenna, J.; Montrose, C.; Wu, E.Y.; Varekamp, P.R.; Stathis, J.H.;

80 nm polysilicon gated n-FETs with ultra-thin Al/sub 2/O/sub 3/ gate dielectric for ULSI applications

2000 / IEEE / 0-7803-6438-4
By: D'Emic, C.; Kozlowski, P.; Bojarczuk, N.; Guha, S.; Copel, M.; Ajmera, A.; Callegari, A.; Mocuta, A.; Gribelyuk, M.A.; Rim, K.; Okorn-Schmidt, H.; Cartier, E.; Gusev, E.P.; Buchanan, D.A.; Arndt, R.; Brown, I.; JAmison, P.C.; Fleming, R.J.; Chan, K.;

Hot carrier lifetime and dielectric breakdown in MOSFETs processed with deuterium

2001 / IEEE / 0-9651577-5-X
By: Cartier, E.; Clark, W.F.; Wu, E.Y.;

Thermally stable ultra-thin Zr silicate for CMOS applications

2001 / IEEE / 0-7803-6412-0
By: Copel, M.; Cartier, E.; Ma, T.P.; Luo, Z.J.; Halpern, B.; Tamagawa, T.;

Ultra-thin ZrO/sub 2/ (or silicate) with high thermal stability for CMOS gate applications

2001 / IEEE / 4-89114-012-7
By: Luo, Z.J.; Ma, T.P.; Halpern, B.; Copel, M.; Tamagawa, T.; Cartier, E.;

Characterization of midgap tungsten gate MOSFETs

2001 / IEEE / 0-7803-7014-7
By: Solomon, P.; Cartier, E.; Guarini, K.W.; White, M.H.; Huiling Shang;

Electrical characterization of Al₂O₃ n-channel MOSFETs with aluminum gates

2001 / IEEE
By: Ragnarsson, L.-A.; Karasinski, J.; Rim, K.; Fischetti, M.V.; Cartier, E.; Bojarczuk, N.A.; Guha, S.;

Electrical characterisation of high-k materials prepared by atomic layer CVD

2001 / IEEE / 4-89114-021-6
By: Carter, R.J.; Cartier, E.; Caymax, M.; De Gendt, S.; Degraevel R; Groeseneken, G.; Young, E.; Kauerauf, T.; Kerber, A.; Kubicek, S.; Lujan, G.; Pantisano, L.; Tsai, W.; Heyns, M.;

Low Weibull slope of breakdown distributions in high-k layers

2002 / IEEE
By: Soens, C.; Cartier, E.; Degraeve, R.; Kauerauf, T.; Groeseneken, G.;

Strong correlation between dielectric reliability and charge trapping in SiO/sub 2//Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

2002 / IEEE / 0-7803-7312-X
By: Kerber, A.; Groeseneken, G.; Roussel, P.; Pantisano, L.; Degraeve, R.; Cartier, E.;

Thermal stability and scalability of Zr-aluminate-based high-k gate stacks

2002 / IEEE / 0-7803-7312-X
By: Maes, J.; Chen, P.J.; Besling, W.F.A.; Copel, M.; Heyns, M.; De Gendt, S.; Vandervorst, W.; Caymax, M.; Kubicek, S.; Bajolet, P.; Young, E.; Tsai, W.; Kerber, A.; Xu, Z.; Cosnier, V.; Petry, J.; Zhao, C.; Kauerauf, T.; Carter, R.J.; Cartier, E.;

Towards understanding degradation and breakdown of SiO₂/high-k stacks

2002 / IEEE / 0-7803-7462-2
By: Kaczer, B.; Blomme, P.; Govoreanu, B.; Cartier, E.; Pantisano, L.; Kauerauf, T.; Degraeve, R.; Groeseneken, G.; Kerber, A.;

Origin of the threshold voltage instability in SiO₂/HfO₂ dual layer gate dielectrics

2003 / IEEE
By: Groeseneken, G.; Cartier, E.; Kerber, A.; Schwalke, U.; Maes, H.E.; Pantisano, L.; Hou, A.; Kim, Y.; Kauerauf, T.; Degraeve, R.;

Stress polarity dependence of degradation and breakdown of SiO/sub 2//high-k stacks

2003 / IEEE / 0-7803-7649-8
By: Pantisano, L.; Roussel, P.; Kerber, A.; Govoreanu, B.; Cartier, E.; Blomme, P.; Kauerauf, T.; Degrave, R.; Groeseneken, G.; Kaczer, B.;

Characterization of the V/sub T/-instability in SiO/sub 2//HfO/sub 2/ gate dielectrics

2003 / IEEE / 0-7803-7649-8
By: Kerber, A.; Schwalke, U.; Maes, H.E.; Groeseneken, G.; Pantisano, L.; Kauerauf, T.; Degraeve, R.; Rosmeulen, M.; Cartier, E.;

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

2003 / IEEE
By: Groeseneken, G.; Kauerauf, T.; Roussel, P.J.; Pantisano, L.; Maes, H.E.; Degraeve, R.; Cartier, E.; Kerber, A.; Schwalke, U.;

Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

2003 / IEEE / 4-89114-033-X
By: Carter, R.J.; Tsai, W.; Onsia, B.; Chen, P.J.; Ragnarsson, L.; Cartier, E.; Heyns, M.; De Gendt, S.; Caymax, M.; Green, M.; Young, E.;

Direct measurement of the inversion charge in MOSFETs: application to mobility extraction in alternative gate dielectrics

2003 / IEEE / 4-89114-033-X
By: Cartier, E.; Kerber, A.; Groeseneken, G.; Kim, Y.; Degraeve, R.; Pantisano, L.; Rosmeulen, M.; Ragnarsson, L.A.;

Dynamics of threshold voltage instability in stacked high-k dielectrics: role of the interfacial oxide

2003 / IEEE / 4-89114-033-X
By: Pantisano, L.; Maes, H.E.; Groeseneken, G.; Rosmeulen, M.; Lorenzini, M.; Degraeve, R.; Kerber, A.; Cartier, E.;

On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

2003 / IEEE
By: Schram, T.; Westlinder, J.; Groeseneken, G.; Olsson, J.; Lujan, G.S.; Kerber, A.; Cartier, E.; Pantisano, L.;

Implementation of high-k gate dielectrics - a status update

2003 / IEEE / 4-89114-037-2
By: De Gendt, S.; Chen, J.; Heyns, M.; Zhao, C.; Young, E.; Witters, T.; Van Elshocht, S.; Rohr, E.; Tsai, W.; Shimamoto, Y.; Schram, T.; Ragnarsson, L.; Puurunen, R.; Pantisano, L.; Niwa, M.; Maes, J.W.; Kubicek, S.; Kerber, A.; Kaushik, V.; Deweerd, W.; Delabie, A.; Conard, T.; Claes, M.; Caymax, M.; Cartier, E.; Carter, R.;

Scaling of high-k dielectrics towards sub-1nm EOT

2003 / IEEE / 0-7803-7765-6
By: Heyns, M.; Beckx, S.; Bender, H.; Blomme, P.; Boullart, W.; Brijs, B.; Carter, R.; Caymax, M.; Claes, M.; Conard, T.; De Gendt, S.; Degraeve, R.; Delabie, A.; Deweerdt, W.; Groeseneken, G.; Henson, K.; Kauerauf, T.; Kubicek, S.; Lucci, L.; Lujan, G.; Mentens, J.; Pantisano, L.; Petry, J.; Richard, O.; Rohr, E.; Schram, T.; Vandervorst, W.; Van Doorne, P.; Van Elshocht, S.; Westlinder, J.; Witters, T.; Zhao, C.; Cartier, E.; Chen, J.; Cosnier, V.; Green, M.; Jang, S.E.; Kaushik, V.; Kerber, A.; Kluth, J.; Lin, S.; Tsai, W.; Young, E.; Manabe, Y.; Shimamoto, Y.; Bajolet, P.; De Witte, H.; Maes, J.W.; Date, L.; Pique, D.; Coenegrachts, B.; Vertommen, J.; Passefort, S.;

Investigation of poly-Si/HfO/sub 2/ gate stacks in a self-aligned 70nm MOS process flow

2003 / IEEE / 0-7803-7999-3
By: Jaenen, P.; Boullart, W.; Pantisano, L.; Kerber, A.; Henson, W.K.; Beckx, S.; Cartier, E.; Lujan, G.S.; Kaushik, V.; Carter, R.J.; Ragnarsson, L.-A.; Chen, J.; Kubicek, S.; De Meyer, K.; Heyns, M.; DeGendt, S.; Caymax, M.;

A study of relaxation current in high-/spl kappa/ dielectric stacks

2004 / IEEE
By: De Gendt, S.; Cartier, E.; Degraeve, R.; Kerber, A.; Heyns, M.; Zhen Xu; Pantisano, L.; Groeseneken, G.;

Characterization of charge trapping in SiO/sub 2//HfO/sub 2/ dielectrics

2003 / IEEE / 0-7803-8139-4
By: Degraeve, R.; Groeseneken, G.; Pantisano, L.; Cartier, E.; Kerber, A.;

Impact of band structure on charge trapping in thin SiO/sub 2//Al/sub 2/O/sub 3//poly-Si gate stacks

2004 / IEEE
By: Cartier, E.; Lucci, L.; Pantisano, L.; Selmi, L.; Green, M.; Groeseneken, G.; Kerber, A.;

Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates

2004 / IEEE / 0-7803-8289-7
By: Jamison, P.; Cabral, C., Jr.; Gusev, E.P.; Narayanan, V.; Cartier, E.; Jammy, R.; Guha, S.; Lacey, D.; Newbury, J.; D'Emic, C.; Carruthers, R.; Linder, B.; Chudzik, M.P.; Gribelyuk, M.; Callegari, A.; Zafar, S.; Cohen, S.A.; Copel, M.; Bojarczuk, N.; Frank, M.; Chan, K.K.; Steen, M.;

Dual work function metal gate CMOS using CVD metal electrodes

2004 / IEEE / 0-7803-8289-7
By: Nakamura, K.; Li, Y.; McFeely, F.R.; Callegari, A.; Narayanan, V.; Shahidi, G.; Ieong, M.; Jammy, R.; Wann, C.; Ng, H.; Duch, F.; Sikorski, E.; Jamison, P.; Lacey, D.; Kawano, Y.; Wajda, C.; Gribelyuk, M.; Cabral, C., Jr.; Milkove, K.; Nguyen, P.; Ku, V.; Steegen, A.; Cartier, E.; Zafar, S.;

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

2005 / IEEE
By: Gusev, E.; Kumar, A.; Zafar, S.; Cartier, E.;

Role of oxygen vacancies in V/sub FB//V/sub t/ stability of pFET metals on HfO/sub 2/

2005 / IEEE / 4-900784-00-1
By: Paruchuri, V.K.; Basker, V.S.; Linder, B.P.; Copel, M.; Jamison, P.; Narayanan, V.; McFeely, F.R.; Cartier, E.; Shahidi, G.; Jammy, R.; Guha, S.; Deligianni, H.; Rubino, J.; Sleight, J.; Steen, M.; Shaw, T.; Carruthers, R.; Lim, D.; Haight, R.;

Systematic study of work function engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks

2005 / IEEE / 0-7803-9268-X
By: Cai, J.; Jammy, R.; Linder, B.; Jamison, P.; Acevedo, J.; Price, B.; Newbury, J.; Narayanan, V.; Natzle, W.; Copel, M.; Zafar, S.; Cartier, E.; Gribelyuk, M.; Gignac, L.; Carruthers, R.; Gusev, E.P.; Cabral, C.; Kim, Y.H.; Ieong, M.;

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

2006 / IEEE
By: Jamison, P.; Gusev, E.P.; Paruchuri, V.K.; Linder, B.P.; Maitra, K.; Narayanan, V.; Frank, M.M.; Lacey, D.L.; Carruthers, R.; Cartier, E.; Arnold, J.; La Tulipe, D.; Steen, M.L.;

Poly-Si/AlN/HfSiO Stack for Ideal Threshold Voltage and Mobility in Sub-100 nm MOSFETs

2006 / IEEE / 1-4244-0005-8
By: Singco, G.; Narayanan, V.; Gribelyuk, M.; Flaitz, P.; Sikorski, E.; Newbury, J.; Kozlowski, P.; Jamison, P.; Steen, M.; Rubino, J.; Wang, X.; Bojarczuk, N.; Linder, B.; Cartier, E.; Paruchuri, V.; Frank, M.M.; Lee, K.L.; Ieong, M.; Jammy, R.; Oldiges, P.; Guha, S.; Zafar, S.;

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

2006 / IEEE / 1-4244-0005-8
By: Paruchuri, V.K.; Bojarczuk, N.A.; Narayanan, V.; Chen, T.C.; Shahidi, G.; Guha, S.; Ieong, M.; Chudzik, M.P.; Jammy, R.; Ronsheim, P.; Batson, P.E.; Wang, Y.; Lacey, D.L.; Locquet, J.-P.; Jamison, P.; Callegari, A.; Cartier, E.; Steen, M.; Copel, M.; Arnold, J.; Brown, S.; Stathis, J.; Zafar, S.; Kim, Y.H.; Doris, B.; Linder, B.P.;

Detection of Hot Electron-Induced Radiation Damage in Organic Dielectrics by Exoelectron Emission from Thin Films

1987 / IEEE
By: Pfluger, P.; Cartier, E.;

Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack

2006 / IEEE / 1-4244-0438-X
By: Linder, B.P.; Cartier, E.; Paruchuri, V.K.; Narayanan, V.;

High-performance high-�/metal gates for 45nm CMOS and beyond with gate-first processing

2007 / IEEE / 978-4-900784-03-1
By: Chudzik, M.; Doris, B.; Chen, T.C.; Khare, M.; Divakaruni, R.; Zhang, Y.; Wise, R.; Narayanan, V.; Takayanagi, M.; Iijima, R.; Ando, T.; Zafar, S.; Wang, X.; Vayshenker, A.; Steen, M.; Stathis, J.; Paruchuri, V.K.; Moumen, N.; Linder, B.; Kim, Y.; He, W.; Hargrove, M.; Gribelyuk, M.; Casarotto, D.; Carter, R.; Callegari, S.; Mo, R.; Sleight, J.; Cartier, E.; Dewan, C.; Park, D.; Bu, H.; Natzle, W.; Yan, W.; Ouyang, C.; Henson, K.; Boyd, D.;

Gate length scaling and high drive currents enabled for high performance SOI technology using high-�/metal gate

2008 / IEEE / 978-1-4244-2377-4
By: Henson, K.; Bu, H.; Khare, M.; Chudzik, M.; Narayanan, V.; Park, D.-G.; Luckowski, E.; Graves-Abe, T.; Wong, K.; Zhang, B.; Bailey, T.; Knarr, R.; Arndt, R.; Harley, E.; Frank, M.; Cartier, E.; Shepard, J.; Yan, W.; Gribelyuk, M.; Wang, X.; Tsang, Y.; Schonenberg, K.; Ramani, K.; Ramachandran, R.; Mo, R.; Na, M.H.; Liang, Y.; Kwon, U.; Krishnan, S.; Schaeffer, J.; Jha, R.; Moumen, N.; Carter, R.; DeWan, C.; Donaton, R.; Guo, D.; Hargrove, M.; He, W.;

TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates

2009 / IEEE / 978-1-4244-2888-5
By: Kerber, A.; Nigam, T.; Krishnan, S.A.; Linder, B.P.; Cartier, E.;

The effect of interface thickness of high-k/metal gate stacks on NFET dielectric reliability

2009 / IEEE / 978-1-4244-2888-5
By: Krishnan, S.; Cartier, E.; Linder, B.P.; Kerber, A.; Stathis, J.H.;

Effects of photoinduced carrier injection on timedependent dielectric breakdown

2009 / IEEE / 978-1-4244-2888-5
By: Cartier, E.; Shaw, T.M.; Lloyd, J.R.; Heinz, T.F.; Laibowitz, R.B.; Atkin, J.M.;

pFET Vt control with HfO2/TiN/poly-Si gate stack using a lateral oxygenation process

2006 / IEEE / 978-1-4244-3308-7
By: Narayanan, V.; Paruchuri, V.K.; Callegari, A.; Choi, C.; Haight, R.; Copel, M.; McFeely, F.R.; Kim, Y.H.; Newbury, J.S.; Frank, M.; Iijima, R.; Ando, T.; Linder, B.P.; Steen, M.; Cartier, E.;

Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond

2006 / IEEE / 978-1-4244-3308-7
By: Choi, C.; Callegari, A.; Jagannathan, H.; Choi, K.; Narayanan, V.; Paruchuri, V.; Iacoponi, J.; Stathis, J.; Brown, S.; Yang, Q.; Edge, L.; Linder, B.; Kerber, A.; Bruley, J.; Zafar, S.; Cartier, E.; Wang, M.; Jamison, P.; Frank, M.; Ando, T.;

Impact of instrumental current scatter on fast Bias Temperature Instability testing

2009 / IEEE / 978-1-4244-3921-8
By: Linder, B.P.; Zhao, K.; Kerber, A.; Cartier, E.;

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

2010 / IEEE / 978-1-4244-5429-7
By: Ioannou, D.P.; Mittl, S.; Wang, Y.; Cartier, E.;

Role of interface layer in stress-induced leakage current in high-k/metal-gate dielectric stacks

2010 / IEEE / 978-1-4244-5429-7
By: Chang, W.L.; Cartier, E.; Stathis, J.H.;

Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs

2010 / IEEE / 978-1-4244-5429-7
By: Kerber, A.; Cartier, E.; Nigam, T.; Lipp, D.; Vayshenker, A.;

A Fast Four-Point Sense Methodology for Extraction of Circuit-Relevant Degradation Parameters

2010 / IEEE
By: Kerber, A.; Cartier, E.;

Interface state density measurements in gated p-i-n silicon nanowires as a function of the nanowire diameter

2010 / IEEE / 978-1-4244-6564-4
By: Sleight, J.W.; Mittal, S.; Gignac, L.M.; Haensch, W.; Cohen, G.M.; Majumdar, A.; Bangsaruntip, S.; Cartier, E.;