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Author: Amos, R.

Results

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
2002 / IEEE / 0-7803-7462-2
By: Carruthers, R.; Cabral, C.; Boyd, D.; Zhang, Y.; Kanarsky, T.; Nowak, E.; Kedzierski, J.; Haensch, W.; Ieong, M.; Wong, H.-S.P.; Cottrell, P.; Fried, D.; Rainey, B.A.; Lee, K.-L.; Krishnan, M.; Canaperi, D.; Wong, K.; Saunders, P.; Benedict, J.; Sullivan, E.; Newbury, J.; Roy, R.; Lavoie, C.; Amos, R.;
Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage
2004 / IEEE / 0-7803-8684-1
By: Gusev, E.P.; Cabral, C., Jr.; Under, B.P.; Kim, Y.H.; Maitra, K.; Carrier, E.; Nayfeh, H.; Amos, R.; Biery, G.; Bojarczuk, N.; Callegari, A.; Carruthers, R.; Cohen, S.A.; Copel, M.; Fang, S.; Frank, M.; Guha, S.; Gribelyuk, M.; Jamison, P.; Jammy, R.; Ieong, M.; Kedzierski, J.; Kozlowski, P.; Ku, K.; Lacey, D.; LaTulipe, D.; Narayanan, V.; Ng, H.; Nguyen, P.; Newbury, J.; Paruchuri, V.; Rengarajan, R.; Shahidi, G.; Steegen, A.; Steen, M.; Zafar, S.; Zhang, Y.;
Design of high performance PFETs with strained si channel and laser anneal
2005 / IEEE / 0-7803-9268-X
By: Luo, Z.; Rim, K.; Ng, H.; Schepis, D.; Amos, R.; Mishra, S.; Lee, J.; Ajmera, A.; Lindsay, R.; Gluschenkov, O.; Turansky, A.; Madan, A.; Davis, R.; Li, J.; Chidambarrao, D.; Holt, J.; Sato, T.; Panda, S.; Greene, B.; Rovedo, N.; Kim, J.; Chong, Y.F.;
High Volume Manufacturing Ramp In 90nm Dual Stress Liner Technology
2006 / IEEE / 1-4244-0254-9
By: Gehres, R.; Malik, R.; Goth, G.; Divakaruni, R.; Yu, C.; Yang, Q.; Wise, R.; Wehella-Gamage, D.; Tetzloff, J.; Tessier, B.; Slisher, D.; Rutten, M.; Van Roijen, R.; Su, T.; Santiago, A.; Rust, T.; Prakash, D.P.; Piper, A.; Patrick, J.; Nastasi, V.; Meyette, E.; Mello, K.; Lindo, P.; Le, N.; Gabor, A.; Davies, B.; Colwill, B.; Collins, C.; Chan, A.; Amos, R.; Brown, J.; Butt, S.;
Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond
2006 / IEEE / 1-4244-0005-8
By: Chen, X.; Fang, S.; Davis, C.; Ku, J.H.; Schiml, T.; Sudijono, J.; Yang, I.; Steegen, A.; Coolbough, D.; Hierlemann, M.; Ng, H.; Amos, R.; Sherony, M.; Belyansky, M.; Widodo, J.; Tjoa, T.; Edleman, N.; Kwon, O.; Panda, S.; Yuan, J.; Nguyen, P.; Nivo, N.; Luo, Z.; Chidambarrao, D.; Stierstorfer, R.; Kim, J.; Gao, W.; Dyer, T.; Teh, Y.W.; Tan, S.S.; Ko, Y.; Baiocco, C.; Ajmera, A.; Park, J.;
A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology
2006 / IEEE / 1-4244-0005-8
By: Yuan, J.; Schiml, T.; Hierlemann, M.; Ku, J.; Sudijono, J.; Ng, K.; Barton, K.; Li, J.; Yang, Z.; Stierstorfer, R.; Rovedo, N.; Dyer, T.; Fang, S.; Lee, W.; Luo, Z.; Amos, R.; Hook, T.; Sardesai, V.; Lindsay, R.; Kim, J.; Lee, Y.M.; Tan, S.S.;
Process induced stress for CMOS performance improvement
2006 / IEEE / 1-4244-0161-5
By: Crowder, S.; Iyer, S.; Ieong, M.; Ng, H.; Amos, R.; Tang, T.J.; Chan, V.; Chen, X.; Yuan, J.; Lun, Z.; Rovedo, N.; Kim, J.J.; Yan, J.; Luo, Z.; Dyer, T.; Tan, S.S.; Fang, S.;
Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices
2006 / IEEE / 1-4244-0438-X
By: Han, J.P.; Utomo, H.; Ieong, M.; Sudijono, J.; Ku, J.H.; Shum, D.; Hierlemann, M.; Amos, R.; Chiulli, G.; Lindsay, R.; Kim, S.D.; Loesing, R.; Burns, L.; Turansky, A.; Madan, A.; St Lawrence, B.; Davis, R.; Murphy, R.; Li, J.; Li, J.; Kim, J.J.; Zhuang, H.; Mishra, S.; Schepis, D.; Gutmann, A.; Teo, L.W.; Rovedo, N.; Luo, Z.; Krishnasamy, R.; Stierstorfer, R.; Chong, Y.F.; Fang, S.; Ng, H.; Holt, J.; Adam, T.N.; Kempisty, J.;

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